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MC68HC08LT8
Data Sheet
M68HC08 Microcontrollers
MC68HC08LT8 Rev. 1 3/2006
freescale.com
MC68HC08LT8
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 3
Revision History
Revision History
Date March, 2006 Revision Level 1 First general release. Description Page Number(s) N/A
MC68HC08LT8 Data Sheet, Rev. 1 4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 3 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Chapter 4 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 5 Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 6 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 7 Programmable Periodic Interrupt (PPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 8 Liquid Crystal Display (LCD) Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Chapter 9 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Chapter 10 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Chapter 11 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Chapter 12 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 13 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Chapter 14 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 151
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List of Chapters
MC68HC08LT8 Data Sheet, Rev. 1 6 Freescale Semiconductor
Table of Contents
Chapter 1 General Description
1.1 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 16 16
Chapter 2 Memory
2.1 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 29 29
Chapter 3 Configuration Register (CONFIG)
3.1 3.2 3.3 3.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 32 33
Chapter 4 System Integration Module (SIM)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Clock Start-up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 37 37 37 37 38 38 38 39 40 40 40 41 41
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Table of Contents
4.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41 41 41 41 41 42 43 44 44 45 45 45 46 46 46 46 46 47 48 48 49 50
Chapter 5 Oscillator (OSC)
5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.4 5.4.1 5.4.2 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1, XTAL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2 & XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 51 52 52 52 52 53 53 53 53
Chapter 6 Timer Interface Module (TIM)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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55 55 55 56 58 58 58 58 59
6.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59 60 61 61 62 62 62 62 62 63 63 63 65 65 66 68
Chapter 7 Programmable Periodic Interrupt (PPI)
7.1 7.2 7.3 7.4 7.5 7.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPI1 Status and Control Register (PPI1SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 71 72 72 73
Chapter 8 Liquid Crystal Display (LCD) Driver
8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.7 8.8 8.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name Conventions and I/O Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Voltages (VLCD, VLCD1, VLCD2, VLCD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Cycle Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Charge and Low Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contrast Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BP0-BP3 (Backplane Drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FP0-FP24 (Frontplane Drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Seven Segment Display Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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75 75 75 77 78 79 79 79 80 80 80 80 81 81 82 86 88 88
Table of Contents
8.8.2 8.8.3
LCD Clock Register (LCDCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LCD Data Registers (LDAT1-LDAT17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Chapter 9 Input/Output (I/O) Ports
9.1 9.2 9.2.1 9.2.2 9.3 9.3.1 9.3.2 9.3.3 9.4 9.4.1 9.4.2 9.5 9.5.1 9.5.2 9.6 9.6.1 9.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Port B High Current Drive Control Register (HDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Chapter 10 External Interrupt (IRQ)
10.1 10.2 10.3 10.3.1 10.4 10.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 107 107 109 109 110
Chapter 11 Keyboard Interrupt Module (KBI)
11.1 11.2 11.3 11.4 11.4.1 11.5 11.5.1 11.5.2 11.6 11.6.1 11.6.2 11.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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111 111 111 112 113 113 114 115 115 115 115 115
Chapter 12 Computer Operating Properly (COP)
12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.4 12.5 12.6 12.7 12.7.1 12.7.2 12.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMGXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 118 118 118 118 118 118 118 119 119 119 119 119 119 119 119
Chapter 13 Low-Voltage Inhibit (LVI)
13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.4 13.5 13.5.1 13.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 121 122 122 123 123 123 124 124 124
Chapter 14 Central Processor Unit (CPU)
14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.4 14.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 11
125 125 125 126 126 127 127 128 129 129
Table of Contents
14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
129 129 129 130 135
Chapter 15 Development Support
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.1 Break Status and Control Register (BRKSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.3 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 137 137 138 138 138 139 139 140 140 141 141 142
Chapter 16 Electrical Specifications
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 143 144 144 145 146 147 148 148 148 149 149
Chapter 17 Ordering Information and Mechanical Specifications
17.1 17.2 17.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MC68HC08LT8 Data Sheet, Rev. 1 12 Freescale Semiconductor
Chapter 1 General Description
1.1 Introduction
The MC68HC08LT8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
1.2 Features
Features include: * High-performance M68HC08 architecture * Fully upward-compatible object code with M6805, M146805, and M68HC05 Families * Low-power design; fully static with stop and wait modes * Maximum internal bus frequency: - 4-MHz at 5-V operating voltage - 2-MHz at 3-V operating voltage * Dual oscillator module - 32.768kHz crystal oscillator - 1 to 16MHz crystal oscillator * 8,192 bytes user read-only memory (ROM) with security(1) * 128 bytes of on-chip random-access memory (RAM) * Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel * Programmable periodic interrupt (PPI) * 4/3 backplanes and static with maximum 24/25 frontplanes liquid crystal display (LCD) driver * Up to 38 general-purpose input/output (I/O) ports: - 4 keyboard interrupt with internal pull up - 2 x 15 mA high current sink pins * System protection features: - Optional computer operating properly (COP) reset - Optional low-voltage detection with reset and selectable trip points for 3-V and 5-V operation - Illegal opcode detection with reset - Illegal address detection with reset * Master reset pin with internal pull-up and power-on reset * IRQ with schmitt-trigger input and programmable pull up * 44-pin low-profile quad flat pack (LQFP)
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the ROM difficult for unauthorized users. MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 13
General Description
*
Specific features in 44-pin package are: - 34 general-purpose I/Os - 4/3 backplanes and static with maximum 20/21 frontplanes liquid crystal display (LCD) driver
Features of the CPU08 include the following: * Enhanced HC05 programming model * Extensive loop control functions * 16 addressing modes (eight more than the HC05) * 16-bit index register and stack pointer * Memory-to-memory data transfers * Fast 8 x 8 multiply instruction * Fast 16/8 divide instruction * Binary-coded decimal (BCD) instructions * Optimization for controller applications * Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC08LT8.
MC68HC08LT8 Data Sheet, Rev. 1 14 Freescale Semiconductor
MCU Block Diagram
INTERNAL BUS M68HC08 CPU CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE PTA7 PTA6 PTA5 PTA4 PTA3/KBI3(2) PTA2/KBI2(2) PTA1/KBI1(2) PTA0/KBI0(2) PTB7/FP2(4) PTB6/FP1(4) PORTB DDRB
CONTROL AND STATUS REGISTERS -- 96 BYTES USER ROM -- 8,192 BYTES USER RAM -- 128 BYTES MONITOR ROM -- 960 BYTES USER ROM VECTOR SPACE -- 48 BYTES OSC MODULE OSC1 OSC2 XTAL1 XTAL2 16-MHz OSCILLATOR
PROGRAMMABLE PERIODIC INTERRUPT MODULE
2-CHANNEL TIMER INTERFACE MODULE 1
2-CHANNEL TIMER INTERFACE MODULE 2
PORTA
DDRA
PTB3/T1CH1(3) PTB2/T1CH0/PPIECK(3) PTB1/T2CH1 PTB0/T2CH0 PTC7 PTC6 PTC5/FP24(4) PTC4/FP23(4) PTC3/FP22 PTC2/FP21 PTC1/FP20 PTC0/FP19
32.768-kHz OSCILLATOR PORTC DDRC SYSTEM INTEGRATION MODULE EXTERNAL INTERRUPT MODULE LIQUID CRYSTAL DISPLAY COMPUTER OPERATING PROPERLY MODULE POWER-ON RESET MODULE LOW-VOLTAGE INHIBIT MODULE DRIVER MODULE
(1)
RST
(1)
IRQ
PTD7/FP18 : PTD0/FP11
PORTD
DDRD
PTE7/FP10 : PTE0/FP3 BP2 : BP0 FP0/BP3
(4)
VLCD VDD VSS POWER (1) Pin contains integrated pullup device. (2) Pin contains integrated pullup device if configured as KBI. (3) High current sink pin, 15mA. (4) Pin not available on 44-pin packages
Figure 1-1. MC68HC08LT8 Block Diagram
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 15
PORTE
DDRE
General Description
1.4 Pin Assignments
PTB2/T1CH0/PPIECK
PTB3/T1CH1
PTB1/T2CH1
PTB0/T2CH0
OSC2
OSC1
44
39
38
37
36
43
42
41
40
35
34
VDD
VSS
BP2
BP1
BP0
FP0/BP3 1 PTE0/FP3 PTE1/FP4 PTE2/FP5 PTE3/FP6 PTE4/FP7 PTE5/FP8 PTE6/FP9 PTE7/FP10 PTD0/FP11 PTD1/FP12 11 PTD2/FP13 12
2 3 4 5 6 7 8 9 10
33
XTAL1 XTAL2 PTA7 PTA6 PTA5 PTA4 PTA3/KBI3 PTA2/KBI2 PTA1/KBI1 PTA0/KBI0
32 31 30 29 28 27 26 25 24 20 13 14 15 16 17 18 19 21
23 22
RST
PTD3/FP14
PTD4/FP15
PTD5/FP16
PTD6/FP17
PTD7/FP18
PTC0/FP19
PTC1/FP20
PTC2/FP21
Pins not available on 44-pin package PTC5/FP24 PTC4/FP23 Internal pads are unconnected PTC7/FP2 PTC6/FP1 VLCD Internal pad connect to VDD -- Set these unused port I/Os to output low
Figure 1-2. 44-Pin LQFP Pin Assignment
MC68HC08LT8 Data Sheet, Rev. 1 16 Freescale Semiconductor
PTC3/FP22
IRQ
Pin Functions
1.5 Pin Functions
Description of the pin functions are provided in Table 1-1. Table 1-1. Pin Functions
Pin Name VDD VSS VLCD RST Power supply Power supply ground LCD bias voltage Reset input, active low; with internal pull up and Schmitt trigger input External IRQ pin; with programmable internal pull up and Schmitt trigger input Used for monitor mode entry OSC1 OSC2 XTAL1 XTAL2 BP0-BP2 BP3/FP0 PTA0/KBI0 PTA1/KBI1 PTA2/KBI2 PTA3/KBI3 PTA4 PTA5 PTA6 PTA7 Crystal input for 16-MHz system clock Crystal oscillator output; inverted OSC1 signal Crystal input for 32.768-kHz for subsystem clock Crystal oscillator output; inverted XTAL1 signal LCD backplane drivers LCD backplane driver BP3 or frontplane driver FP0 8-bit general-purpose I/O port Pin Description Input/Output Input Output Input Input/output Input Input Input Output Input Output Output Output Input/output Voltage Level 5 V or 3 V 0V VDD VDD VDD VDD to VTST VDD VDD VDD VDD VDD VDD VDD
IRQ
PTA0-PTA3 as keyboard interrupts with pull-up device, KBI0-KBI3
Input
VDD
8-bit general-purpose I/O port, with high current sinks on PTB2-PTB3 PTB0/T2CH0 PTB1/T2CH1 PTB2/T1CH0/PPIECK PTB3/T1CH1 PTB6/FP1 PTB7/FP2 PTB0 as T2CH0 of TIM2 PTB1 as T2CH1 of TIM2 PTB2 as PPIECK; external clock source input for PPI PTB2 as T1CH0 of TIM1 PTB3 as T1CH1 of TIM1 PTB6-PTB7 as LCD frontplane drivers, FP1-FP2
Input/output Input/output Input/output Input Input/output Input/output Output
VDD VDD VDD VDD VDD VDD VDD
Continued on next page
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 17
General Description
Table 1-1. Pin Functions (Continued)
Pin Name PTC0/FP19 PTC1/FP20 PTC2/FP21 PTC3/FP22 PTC4/FP23 PTC5/FP24 PTC6 PTC7 PTD0/FP11 PTD1/FP12 PTD2/FP13 PTD3/FP14 PTD4/FP15 PTD5/FP16 PTD6/FP17 PTD7/FP18 PTE0/FP3 PTE1/FP4 PTE2/FP5 PTE3/FP6 PTE4/FP7 PTE5/FP8 PTE6/FP9 PTE7/FP10 Pin Description 8-bit general-purpose I/O port Input/Output Input/output Voltage Level VDD
PTC0-PTC5 as LCD frontplane drivers, FP19-FP24
Output
VDD
8-bit general-purpose I/O port
Input/output
VDD
PTD0-PTD7 as LCD frontplane drivers, FP11-FP18
Output
VDD
8-bit general-purpose I/O port
Input/output
VDD
PTE0-PTE7 as LCD frontplane drivers, FP3-FP10
Output
VDD
MC68HC08LT8 Data Sheet, Rev. 1 18 Freescale Semiconductor
Chapter 2 Memory
2.1 Introduction
The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes: * 8,192 bytes of user read-only memory (ROM) * 128 bytes of random-access memory (RAM) * 48 bytes of user-defined vectors * 960 bytes of monitor ROM
2.2 I/O Section
Addresses $0000-$007F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: * $FE0F; Low-voltage inhibit status register, LVISR * $FFFF; COP control register, COPCTL
2.3 Monitor ROM
The 350 bytes at addresses $FE20-$FF7D are reserved ROM addresses that contain the instructions for the monitor functions.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 19
Memory
$0000 $007F $0080 $00FF $0100 $0B96 $0B97 $0DEF $0DF0 $DDFF $DE00 $FDFF $FE00 $FE0E $FE0F $FE10 $FE1F $FE20 $FF7D $FF7E $FF7F $FF96 $FF97 $FFCF $FFD0 $FFFF
I/O REGISTERS 128 BYTES RAM 128 BYTES UNIMPLEMENTED 2,711 BYTES RESERVED FOR MONITOR ROM 601 BYTES UNIMPLEMENTED 53,264 BYTES User ROM 8,192 BYTES SYSTEM REGISTERS 15 BYTES LVI STATUS REGISTER (LVISR) UNIMPLEMENTED 16 BYTES MONITOR ROM 350 BYTES UNIMPLEMENTED MONITOR JUMP TABLE 24 BYTES UNIMPLEMENTED 57 BYTES USER ROM VECTORS 48 BYTES
Figure 2-1. Memory Map
MC68HC08LT8 Data Sheet, Rev. 1 20 Freescale Semiconductor
Monitor ROM
Addr.
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: Read: Data Direction Register A Write: (DDRA) Reset: Read: Data Direction Register B Write: (DDRB) Reset: Read: Data Direction Register C Write: (DDRC) Reset: Read: Data Direction Register D Write: (DDRD) Reset: Read: Data Direction Register E Write: (DDRE) Reset: Read: Port E Data Register Write: (PTE) Reset:
Bit 7 PTA7
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
$0000
Unaffected by reset 0 PTB7 PTB6 0 PTB3 Unaffected by reset PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 PTB2 PTB1 PTB0
$0001
$0002
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA7 0 DDRB7 0 DDRC7 0 DDRD7 0 DDRE7 0 PTE7 DDRA6 0 DDRB6 0 DDRC6 0 DDRD6 0 DDRE6 0 PTE6 0 DDRC5 0 DDRD5 0 DDRE5 0 PTE5 0 DDRC4 0 DDRD4 0 DDRE4 0 PTE4 DDRA5 0 0 DDRA4 0 0 DDRB3 0 DDRC3 0 DDRD3 0 DDRE3 0 PTE3 DDRB2 0 DDRC2 0 DDRD2 0 DDRE2 0 PTE2 DDRB1 0 DDRC1 0 DDRD1 0 DDRE1 0 PTE1 DDRB0 0 DDRC0 0 DDRD0 0 DDRE0 0 PTE0 DDRA3 0 DDRA2 0 DDRA1 0 DDRA0 0
$0004
$0005
$0006
$0007
$0008
$0009
Unaffected by reset
$000A
Unimplemented
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 21
Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
$000B
Unimplemented
$000C
Read: Port-B High Current Drive Control Register Write: (HDB) Reset:
0
0
0
0 HDB3 HDB2 0
0
0
0
0
0
0
0
0
0
$000D $0018
Unimplemented
$0019
Read: PPI1 Status and Control Register Write: (PPI1SCR) Reset:
0 PPI1L 0 PPI1MSK 0 PPICLKS1 PPI1CLKS0 1 0 0 PPI1IE2 0 PPI1IE1 0 PPI1IE0 0
$001A
Unimplemented
Keyboard Status and Control Read: Register $001B Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset:
KEYF R 0 0 R 0 0 R 0 0 R
0 IMASKK ACKK MODEK 0 KBIE0 0 LVISEL0 1(2) MODE 0 COPD 0
0 0
0 KBIE3
0 KBIE2 0 PCEL 0 0
0 KBIE1 0 LVISEL1 0(2) IMASK
$001C
0
0 STOP_ XTALEN 0 0
0 PEE 0 0
0 PDE 0 0
0 PCEH 0 IRQF
$001D
Read: STOP_ Configuration Register 2 Write: XCLKEN (CONFIG2)(1) Reset: 0 Read: IRQ Status and Control Register Write: (INTSCR) Reset: Read: Configuration Register 1 Write: (CONFIG1)(1) Reset: 0
$001E
ACK 0 COPRS 0 0 LVISTOP 0 0 LVIRSTD 0 0 LVIPWRD 0(2) 0 R 0 0 SSREC 0 0 STOP 0
$001F
1. One-time writable register after each reset. 2. One time writable after each POR and reset by POR only. U = Unaffected X = Indeterminate = Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
MC68HC08LT8 Data Sheet, Rev. 1 22 Freescale Semiconductor
Monitor ROM Addr. Register Name Read: Timer 1 Status and Control Register Write: (T1SC) Reset: Read: Timer 1 Counter Register High Write: (T1CNTH) Reset: Read: Timer 1 Counter Register Low Write: (T1CNTL) Reset: Read: Timer 1 Counter Modulo Register High Write: (T1MODH) Reset: Read: Timer 1 Counter Modulo Register Low Write: (T1MODL) Reset: Bit 7 TOF TOIE 0 0 Bit 15 0 14 1 13 TSTOP TRST 0 12 0 11 0 10 0 9 0 Bit 8 6 5 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
$0020
$0021
0 Bit 7
0 6
0 5
0 4
0 3
0 2
0 1
0 Bit 0
$0022
0 Bit 15 1 Bit 7 1 CH0F
0 14 1 6 1 CH0IE
0 13 1 5 1 MS0B 0 13
0 12 1 4 1 MS0A 0 12
0 11 1 3 1 ELS0B 0 11
0 10 1 2 1 ELS0A 0 10
0 9 1 1 1 TOV0 0 9
0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$0023
$0024
Read: Timer 1 Channel 0 Status and $0025 Control Register Write: (T1SC0) Reset: Read: Timer 1 Channel 0 Register High Write: (T1CH0H) Reset: Read: Timer 1 Channel 0 Register Low Write: (T1CH0L) Reset:
0 0 Bit 15 0 14
$0026
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0027
Indeterminate after reset CH1F CH1IE 0 0 Bit 15 0 14 0 13 0 12 0 11 0 10 0 9 0 Bit 8 0 MS1A ELS1B ELS1A TOV1 CH1MAX
Read: Timer 1 Channel 1 Status and $0028 Control Register Write: (T1SC1) Reset: Read: Timer 1 Channel 1 Register High Write: (T1CH1H) Reset: Read: Timer 1 Channel 1 Register Low Write: (T1CH1L) Reset: U = Unaffected
$0029
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$002A
Indeterminate after reset X = Indeterminate = Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 23
Memory Addr. Register Name Read: Timer 2 Status and Control Register Write: (T2SC) Reset: Read: Timer 2 Counter Register High Write: (T2CNTH) Reset: Read: Timer 2 Counter Register Low Write: (T2CNTL) Reset: Read: Timer 2 Counter Modulo Register High Write: (T2MODH) Reset: Read: Timer 2 Counter Modulo Register Low Write: (T2MODL) Reset: Bit 7 TOF TOIE 0 0 Bit 15 0 14 1 13 TSTOP TRST 0 12 0 11 0 10 0 9 0 Bit 8 6 5 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
$002B
$002C
0 Bit 7
0 6
0 5
0 4
0 3
0 2
0 1
0 Bit 0
$002D
0 Bit 15 1 Bit 7 1 CH0F
0 14 1 6 1 CH0IE
0 13 1 5 1 MS0B 0 13
0 12 1 4 1 MS0A 0 12
0 11 1 3 1 ELS0B 0 11
0 10 1 2 1 ELS0A 0 10
0 9 1 1 1 TOV0 0 9
0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$002E
$002F
Read: Timer 2 Channel 0 Status and $0030 Control Register Write: (T2SC0) Reset: Read: Timer 2 Channel 0 Register High Write: (T2CH0H) Reset: Read: Timer 2 Channel 0 Register Low Write: (T2CH0L) Reset:
0 0 Bit 15 0 14
$0031
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0032
Indeterminate after reset CH1F CH1IE 0 0 Bit 15 0 14 0 13 0 12 0 11 0 10 0 9 0 Bit 8 0 MS1A ELS1B ELS1A TOV1 CH1MAX
Read: Timer 2 Channel 1 Status and $0033 Control Register Write: (T2SC1) Reset: Read: Timer 2 Channel 1 Register High Write: (T2CH1H) Reset: Read: Timer 2 Channel 1 Register Low Write: (T2CH1L) Reset: U = Unaffected
$0034
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0035
Indeterminate after reset X = Indeterminate = Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
MC68HC08LT8 Data Sheet, Rev. 1 24 Freescale Semiconductor
Monitor ROM Addr. $0036 $004E Register Name Bit 7 6 5 4 3 2 1 Bit 0
Unimplemented
$004F
Read: LCD Clock Register Write: (LCDCLK) Reset: Read:
0 FCCTL1 0 R 0 R FCCTL0 0 R DUTY1 0 R DUTY0 0 R LCLK2 0 R LCLK1 0 R LCLK0 0 R
$0050
Reserved Write: Reset: Read: LCD Control Register Write: (LCDCR) Reset: Read: LCD Data Register Write: (LDAT1) Reset: Read: LCD Data Register Write: (LDAT2) Reset: Read: LCD Data Register Write: (LDAT3) Reset: Read: LCD Data Register Write: (LDAT4) Reset: Read: LCD Data Register Write: (LDAT5) Reset: Read: LCD Data Register Write: (LDAT6) Reset: Read: LCD Data Register Write: (LDAT7) Reset: U = Unaffected 0 LCDE 0 F1B3 U F3B3 U F5B3 U F7B3 U F9B3 U F11B3 U F13B3 U X = Indeterminate 0 F1B2 U F3B2 U F5B2 U F7B2 U F9B2 U F11B2 U F13B2 U FC 0 F1B1 U F3B1 U F5B1 U F7B1 U F9B1 U F11B1 U F13B1 U LC 0 F1B0 U F3B0 U F5B0 U F7B0 U F9B0 U F11B0 U F13B0 U = Unimplemented LCCON3 0 F0B3 U F2B3 U F4B3 U F6B3 U F8B3 U F10B3 U F12B3 U LCCON2 0 F0B2 U F2B2 U F4B2 U F6B2 U F8B2 U F10B2 U F12B2 U R LCCON1 0 F0B1 U F2B1 U F4B1 U F6B1 U F8B1 U F10B1 U F12B1 U = Reserved LCCON0 0 F0B0 U F2B0 U F4B0 U F6B0 U F8B0 U F10B0 U F12B0 U
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 25
Memory Addr. Register Name Read: LCD Data Register Write: (LDAT8) Reset: Read: LCD Data Register Write: (LDAT9) Reset: Read: LCD Data Register Write: (LDAT10) Reset: Read: LCD Data Register Write: (LDAT11) Reset: Read: LCD Data Register Write: (LDAT12) Reset: Read: LCD Data Register Write: (LDAT13) Reset: Bit 7 F15B3 U F17B3 U F19B3 U F21B3 U F23B3 U 0 6 F15B2 U F17B2 U F19B2 U F21B2 U F23B2 U 0 5 F15B1 U F17B1 U F19B1 U F21B1 U F23B1 U 0 4 F15B0 U F17B0 U F19B0 U F21B0 U F23B0 U 0 F24B3 0 0 0 0 U F24B2 U F24B1 U F24B0 U 3 F14B3 U F16B3 U F18B3 U F20B3 U F22B3 U 2 F14B2 U F16B2 U F18B2 U F20B2 U F22B2 U 1 F14B1 U F16B1 U F18B1 U F20B1 U F22B1 U Bit 0 F14B0 U F16B0 U F18B0 U F20B0 U F22B0 U
$0059
$005A
$005B
$005C
$005D
$005E
$005F $007F
Unimplemented
$FE00
Read: Break Status Register Write: (SBSR) Reset:
SBSW R R R R R R See note 0 R
Note: Writing a logic 0 clears SBSW. Read: Reset Status Register Write: (SRSR) POR: POR PIN COP ILOP ILAD 0 LVI 0
$FE01
1 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
$FE02
Reserved
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
MC68HC08LT8 Data Sheet, Rev. 1 26 Freescale Semiconductor
Monitor ROM Addr. Register Name Read: Break Flag Control Register Write: (SBFCR) Reset: Read: Interrupt Status Register 1 Write: (INT1) Reset: Read: Interrupt Status Register 2 Write: (INT2) Reset: Read: Interrupt Status Register 3 Write: (INT3) Reset: Bit 7 BCFE 0 IF6 R 0 0 R 0 0 R 0 R Reserved IF5 R 0 0 R 0 0 R 0 R IF4 R 0 0 R 0 0 R 0 R IF3 R 0 0 R 0 0 R 0 R IF2 R 0 IF10 R 0 0 R 0 R IF1 R 0 IF9 R 0 0 R 0 R 0 R 0 IF8 R 0 IF16 R 0 R 0 R 0 IF7 R 0 0 R 0 R 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
$FE03
$FE04
$FE05
$FE06
$FE07 $FE0B
$FE0C
Read: Break Address Register High Write: (BRKH) Reset:
Bit 15 0 Bit 7 0 BRKE 0 LVIOUT
14 0 6 0 BRKA 0 LVIIE
13 0 5 0 0
12 0 4 0 0
11 0 3 0 0
10 0 2 0 0
9 0 1 0 0
Bit 8 0 Bit 0 0 0
Read: Break Address Register Low $FE0D Write: (BRKL) Reset: Read: Break Status and Control Register Write: (BRKSCR) Reset: Read: Low-Voltage Inhibit Status Register Write: (LVISR) Reset:
$FE0E
0 LVIIF
0 0 LVIIAK
0 0
0 0
0 0
0 0
$FE0F
0
0
0
0
0
0
0
0
$FFFF
Read: COP Control Register Write: (COPCTL) Reset: U = Unaffected X = Indeterminate
Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 27
Memory
Table 2-1. Vector Addresses
Vector Priority Lowest IF16 $FFDD -- $FFDE $FFE9 $FFE8 IF10 $FFE9 $FFEA IF9 $FFEB $FFEC IF8 $FFED $FFEE IF7 $FFEF $FFF0 IF6 $FFF1 $FFF2 IF5 $FFF3 $FFF4 IF4 $FFF5 $FFF6 IF3 $FFF7 $FFF8 IF2 $FFF9 $FFFA IF1 $FFFB $FFFC -- $FFFD $FFFE -- Highest $FFFF Reset SWI IRQ LVI Not used TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow PPI1 Not used INT Flag Address $FFDC KBI Vector
.
MC68HC08LT8 Data Sheet, Rev. 1 28 Freescale Semiconductor
Random-Access Memory (RAM)
2.4 Random-Access Memory (RAM)
The 512 bytes RAM are located from $0080 through $027F. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
2.5 Read-Only Memory (ROM)
The 8,192 bytes user ROM are located from $DE00 through $FDFF, plus a block of 48 bytes for user interrupt vectors from $FFD0 through $FFFF.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 29
Memory
MC68HC08LT8 Data Sheet, Rev. 1 30 Freescale Semiconductor
Chapter 3 Configuration Register (CONFIG)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: * Computer operating properly module (COP) * COP timeout period (213 -24 or 218 -24 CGMXCLK cycles) * Crystal oscillators during stop mode * Low voltage inhibit (LVI) module power * LVI module reset * LVI module in stop mode * LVI module voltage trip point selection * STOP instruction * Stop mode recovery time (32 or 4096 CGMXCLK cycles) * LCD frontplanes FP3-FP10 on port E * LCD frontplanes FP11-FP18 on port D * LCD frontplanes FP19-FP24 on port C
Addr. $001D
Register Name
Bit 7
6 STOP_ XTALEN 0 LVISTOP 0
5 PEE 0 LVIRSTD 0
4 PDE 0 LVIPWRD 0(2)
3 PCEH 0 R 0
2 PCEL 0 SSREC 0
1 LVISEL1 0(2) STOP 0
Bit 0 LVISEL0 1(2) COPD 0
Read: STOP_ Configuration Register 2 Write: XCLKEN (CONFIG2)(1) Reset: 0 Read: Configuration Register 1 Write: (CONFIG1)(1) Reset: COPRS 0
$001F
1. One-time writable register after each reset. 2. LVIT1, LVIT0, and LVIPWRD reset to 0 by a power-on reset (POR) only. R = Reserved
Figure 3-1. CONFIG Registers Summary
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 31
Configuration Register (CONFIG)
3.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001D and $001F. The configuration registers may be read at anytime. NOTE The options except LVIT[1:0] and LVIPWRD are one-time writable by the user after each reset. The LVIT[1:0] and LVIPWRD bits are one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 3-2 and Figure 3-3. The mask option register (MOR) is used to select the oscillator option for the MCU: crystal oscillator or RC oscillator. The MOR is implemented as a byte in FLASH memory. Hence, writing to the MOR requires programming the byte.
3.3 Configuration Register 1 (CONFIG1)
Address: $001F Bit 7 Read: Write: Reset: POR: COPRS 0 0 R 6 LVISTOP 0 0 = Reserved 5 LVIRSTD 0 0 4 LVIPWRD U 0 U = Unaffected 3 R 0 0 2 SSREC 0 0 1 STOP 0 0 Bit 0 COPD 0 0
Figure 3-2. Configuration Register 1 (CONFIG1) COPRS -- COP Rate Select COPRS selects the COP time-out period. Reset clears COPRS. 1 = COP timeout period is (213 - 24) CGMXCLK cycles 0 = COP timeout period is (218 - 24) CGMXCLK cycles LVISTOP -- Low Voltage Inhibit Enable in Stop Mode When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD -- Low Voltage Inhibit Reset Disable LVIRSTD disables the reset signal from the LVI module. Reset clears LVIRSTOP. 1 = LVI module reset disabled 0 = LVI module reset enabled
MC68HC08LT8 Data Sheet, Rev. 1 32 Freescale Semiconductor
Configuration Register 2 (CONFIG2)
LVIPWRD -- Low Voltage Inhibit Power Disable LVIPWRD disables the LVI module. This bit is reset to 0 by a POR only. 1 = LVI module disabled 0 = LVI module enabled NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay. 1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. Reset clears COPD. 1 = COP module disabled 0 = COP module enabled
3.4 Configuration Register 2 (CONFIG2)
Address: $001D Bit 7 Read: Write: Reset: POR: STOP_ XCLKEN 0 0 R 6 STOP_ XTALEN 0 0 = Reserved 5 PEE 0 0 4 PDE 0 0 U = Unaffected 3 PCEH 0 0 2 PCEL 0 0 1 LVISEL1 U 0 Bit 0 LVISEL0 U 1
Figure 3-3. Configuration Register 2 (CONFIG2) STOP_XCLKEN -- Crystal Oscillator Stop Mode Enable (OSC) Setting STOP_XCLKEN enables the crystal oscillator on OSC1 and OSC2 to continue operating during stop mode. Reset clears this bit. 1 = Crystal oscillator enabled on OSC pins during stop mode 0 = Crystal oscillator disabled on OSC pins during stop mode STOP_XTALEN -- Crystal Oscillator Stop Mode Enable (XTAL) Setting STOP_XTALEN enables the crystal oscillator on XTAL1 and XTAL2 to continue operating during stop mode. Reset clears this bit. 1 = Crystal oscillator enabled on XTAL pins during stop mode 0 = Crystal oscillator disabled on XTAL pins during stop mode
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 33
Configuration Register (CONFIG)
PEE -- Port E Enable for LCD Drive Setting PEE configures the PTE0/FP3-PTE7/FP10 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTE0/FP3-PTE7/FP10 pins configured as LCD frontplane driver pins: FP3-FP10 0 = PTE0/FP3-PTE7/FP10 pins configured as standard I/O pins: PTE0-PTE7 PDE -- Port D Enable for LCD Drive Setting PDE configures the PTD0/FP11-PTD7/FP18 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTD0/FP11-PTD7/FP18 pins configured as LCD frontplane driver pins: FP11-FP18 0 = PTD0/FP11-PTD7/FP18 pins configured as standard I/O pins: PTD0-PTD7 PCEH -- Port C High Nibble Enable for LCD Drive Setting PCEH configures the PTC4/FP23-PTC5/FP24 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTC4/FP23-PTC5/FP24 pins configured as LCD frontplane driver pins: FP23-FP24 0 = PTC4/FP23-PTC5/FP24 pins configured as standard I/O pins: PTC4-PTC5 PCEL -- Port C Low Nibble Enable for LCD Drive Setting PCEL configures the PTC0/FP19-PTC3/FP22 pins for LCD frontplane driver use. Reset clears this bit. 1 = PTC0/FP19-PTC3/FP22 pins configured as LCD frontplane driver pins: FP19-FP22 0 = PTC0/FP19-PTC3/FP22 pins configured as standard I/O pins: PTC0-PTC3 LVISEL1, LVISEL0 -- LVI Trip Voltage Selection These two bits determine at which level of VDD the LVI module will come into action. LVISEL1 and LVISEL0 are set to the default configuration by a power-on reset only. Table 3-1. Trip Voltage Selection
LVISEL1 0 0 1 1 LVISEL0 0 1 0 1 Comments(1) Reserved For VDD = 3 V operation (default after POR) For VDD = 5 V operation Reserved
1. See Chapter 16 Electrical Specifications for full parameters.
MC68HC08LT8 Data Sheet, Rev. 1 34 Freescale Semiconductor
Chapter 4 System Integration Module (SIM)
4.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals: - Stop/wait/reset/break entry and recovery - Internal clock control * Master reset control, including power-on reset (POR) and COP timeout * Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * CPU enable/disable timing * Modular architecture expandable to 128 interrupt sources
Table 4-1. Signal Name Conventions
Signal Name CGMXCLK IAB IDB PORRST IRST R/W Oscillator clock from oscillator module Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal Description
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 35
System Integration Module (SIM)
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSC) SIM COUNTER COP CLOCK
CGMXCLK (FROM OSC) CGMXCLK (FROM OSC) /2
VDD INTERNAL PULLUP DEVICE RESET PIN LOGIC
CLOCK CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 4-1. SIM Block Diagram
Addr. $FE00 Register Name Read: Break Status Register Write: (BSR) Reset: Read: Reset Status Register Write: (RSR) POR: Reserved Read: Break Flag Control Write: Register (BFCR) Reset: Bit 7 R 0 POR 1 R BCFE 0 6 R 0 PIN 0 R R 5 R 0 COP 0 R R 4 R 0 ILOP 0 R R 3 R 0 ILAD 0 R R 2 R 0 MODRST 0 R R 1 SBSW NOTE 0 LVI 0 R R Bit 0 R 0 0 0 R R
Note: Writing a 0 clears SBSW. $FE01 $FE02 $FE03
Figure 4-2. SIM I/O Register Summary
MC68HC08LT8 Data Sheet, Rev. 1 36 Freescale Semiconductor
SIM Bus Clock Control and Generation Addr. $FE04 Register Name Read: Interrupt Status Register 1 Write: (INT1) Reset: Read: Interrupt Status Register 2 Write: (INT2) Reset: Read: Interrupt Status Register 3 Write: (INT3) Reset: Bit 7 IF6 R 0 0 R 0 0 R 0 6 IF5 R 0 0 R 0 0 R 0 = Unimplemented 5 IF4 R 0 0 R 0 0 R 0 4 IF3 R 0 0 R 0 0 R 0 3 IF2 R 0 IF10 R 0 0 R 0 R 2 IF1 R 0 IF9 R 0 0 R 0 = Reserved 1 0 R 0 IF8 R 0 IF16 R 0 Bit 0 0 R 0 IF7 R 0 0 R 0
$FE05
$FE06
Figure 4-2. SIM I/O Register Summary (Continued)
4.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMXCLK as shown in Figure 4-3. This clock can come from either the oscillator module or from the on-chip PLL. (See Chapter 5 Oscillator (OSC).)
SIM COUNTER OSCXCLK
/2
CGMXCLK
/2
BUS CLOCK GENERATORS
OSC
SIM
Figure 4-3. SIM Clock Signals
4.2.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four.
4.2.2 Clock Start-up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout.
4.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 4.6.2 Stop Mode.)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 37
System Integration Module (SIM)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
4.3 Reset and System Initialization
The MCU has these reset sources: * Power-on reset module (POR) * External reset pin (RST) * Computer operating properly module (COP) * Low-voltage inhibit module (LVI) * Illegal opcode * Illegal address All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 4.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 4.7 SIM Registers.)
4.3.1 External Pin Reset
The RST pin circuit includes an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 4-2 for details. Figure 4-4 shows the relative timing. Table 4-2. PIN Bit Set Timing
Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
CGMXCLK
RST
IAB
PC
VECT H VECT L
Figure 4-4. External Reset Timing
4.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 4-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 4-6).
MC68HC08LT8 Data Sheet, Rev. 1 38 Freescale Semiconductor
Reset and System Initialization
NOTE For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 4-5.
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 4-5. Internal Reset Timing The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR
INTERNAL RESET
Figure 4-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 4.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, these events occur: * A POR pulse is generated. * The internal reset signal is asserted. * The SIM enables CGMXCLK. * Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. * The RST pin is driven low during the oscillator stabilization time. * The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 39
System Integration Module (SIM)
OSC1
PORRST 4096 CYCLES CGMXCLK 32 CYCLES 32 CYCLES
RST IRST
IAB
$FFFE
$FFFF
Figure 4-7. POR Recovery 4.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every 213 - 24 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. 4.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 4.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
MC68HC08LT8 Data Sheet, Rev. 1 40 Freescale Semiconductor
SIM Counter
4.3.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 4.3.2.6 Monitor Mode Entry Module Reset (MODRST) The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are blank ($FF). (See Chapter 15 Development Support.) When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources.
4.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
4.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator module (OSC) to drive the bus clock state machine.
4.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared.
4.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 4.6.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 4.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.)
4.5 Exception Control
Normal, sequential program execution can be changed in three different ways: * Interrupts: - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 41
System Integration Module (SIM)
* *
Reset Break interrupts
4.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 4-8 shows interrupt entry timing, and Figure 4-9 shows interrupt recovery timing.
MODULE INTERRUPT I-BIT IAB IDB R/W DUMMY DUMMY SP SP - 1 SP - 2 X SP - 3 A SP - 4 CCR VECT H VECT L START ADDR OPCODE
PC - 1[7:0] PC - 1[15:8]
V DATA H
V DATA L
Figure 4-8. Interrupt Entry Timing
MODULE INTERRUPT I-BIT IAB IDB R/W SP - 4 CCR SP - 3 A SP - 2 X SP - 1 SP PC PC + 1 OPCODE OPERAND
PC - 1[15:8] PC - 1[7:0]
Figure 4-9. Interrupt Recovery Timing Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 4-10.)
MC68HC08LT8 Data Sheet, Rev. 1 42 Freescale Semiconductor
Exception Control
FROM RESET
BREAK I BIT SET? INTERRUPT? NO YES
YES
I-BIT SET? NO IRQ INTERRUPT? NO YES
AS MANY INTERRUPTS AS EXIST ON CHIP
STACK CPU REGISTERS SET I-BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO RTI INSTRUCTION? NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 4-10. Interrupt Processing 4.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 4-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 43
System Integration Module (SIM)
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 4-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 4.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
4.5.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 2-1 summarizes the interrupt sources and the interrupt status register flags that they set.
MC68HC08LT8 Data Sheet, Rev. 1 44 Freescale Semiconductor
Exception Control
4.5.2.1 Interrupt Status Register 1
Address: Read: Write: Reset: $FE04 Bit 7 IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 4-12. Interrupt Status Register 1 (INT1) IF6-IF1 -- Interrupt Flags 1-6 These flags indicate the presence of interrupt requests from the sources shown in Table 2-1. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 -- Always read 0 4.5.2.2 Interrupt Status Register 2
Address: Read: Write: Reset: $FE05 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 IF10 R 0 2 IF9 R 0 1 IF8 R 0 Bit 0 IF7 R 0
Figure 4-13. Interrupt Status Register 2 (INT2) IF10-IF7 -- Interrupt Flags 10-7 These flags indicate the presence of interrupt requests from the sources shown in Table 2-1. 1 = Interrupt request present 0 = No interrupt request present 4.5.2.3 Interrupt Status Register 3
Address: Read: Write: Reset: $FE06 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 IF16 R 0 Bit 0 0 R 0
Figure 4-14. Interrupt Status Register 3 (INT3) IF16 -- Interrupt Flag 16 This flag indicates the presence of an interrupt request from the source shown in Table 2-1. 1 = Interrupt request present 0 = No interrupt request present
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 45
System Integration Module (SIM)
4.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
4.5.4 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
4.5.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initialize the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
4.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
4.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 4-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
MC68HC08LT8 Data Sheet, Rev. 1 46 Freescale Semiconductor
Low-Power Modes
IAB WAIT ADDR WAIT ADDR + 1 SAME SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 4-15. Wait Mode Entry Timing Figure 4-16 and Figure 4-17 show the timing for WAIT recovery.
IAB $6E0B $6E0C $00FF $00FE $00FD $00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 4-16. Wait Recovery from Interrupt or Break
32 CYCLES IAB $6E0B 32 CYCLES RST VCT H RST VCT L
IDB
$A6
$A6
$A6
RST
CGMXCLK
Figure 4-17. Wait Recovery from Internal Reset
4.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator output (CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR).
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 47
System Integration Module (SIM)
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 4-18 shows stop mode entry timing. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 4-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 4-19. Stop Mode Recovery from Interrupt or Break
4.7 SIM Registers
The SIM has three memory-mapped registers: * SIM Break Status Register (SBSR) * SIM Reset Status Register (SRSR) * SIM Break Flag Control Register (SBFCR)
4.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode.
MC68HC08LT8 Data Sheet, Rev. 1 48 Freescale Semiconductor
SIM Registers
Address: $FE00 Bit 7 Read: Write: Reset: R = Reserved 1. Writing a clears SBSW. R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) 0 Bit 0 R
Figure 4-20. Break Status Register (BSR) SBSW -- Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it. The following code is an example.
This code works if the H register has been pushed onto the stack in the break service routine software. This code should be executed at the end of the break service routine software. HIBYTE LOBYTE EQU EQU If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register.
4.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register
Address: $FE01 Bit 7 Read: Write: POR: 1 0 = Unimplemented 0 0 0 0 0 0 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 0 1 LVI Bit 0 0
Figure 4-21. Reset Status Register (RSR)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 49
System Integration Module (SIM)
POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR
4.7.3 SIM Break Flag Control Register
Address: $FE03 Bit 7 Read: Write: Reset: BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 4-22. Break Flag Control Register (BFCR) The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state. BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
MC68HC08LT8 Data Sheet, Rev. 1 50 Freescale Semiconductor
Chapter 5 Oscillator (OSC)
5.1 Introduction
The oscillator module provides the reference clocks for the MCU system and bus. Two oscillators are running on the device: * 1-16MHz crystal oscillator (OSC) -- built-in oscillator that requires an external crystal or ceramic-resonator. This oscillator drives the main bus and other MCU subsystems except the LCD and PPI modules. * 32.768kHz crystal oscillator (XTAL) -- built-in oscillator that requires an external crystal or ceramic-resonator. This oscillator drives the LCD and PPI modules.
5.2 Functional Overview
The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 5-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * Crystal, X1 & X2 * Fixed capacitor, C1 & C3 * Tuning capacitor, C2 & C4 (can also be a fixed capacitor) * Feedback resistor, RB1 & RB2 * Series resistor, RS (for XTAL1 and XTAL2 only)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 51
Oscillator (OSC)
From SIM SIMOSCEN CONFIG2 STOP_XTALEN CONFIG2 STOP_XCLKEN OSCXCLK /2 To all Modules CGMXCLK To LCD and PPI Modules 32KXCLK
MCU OSC1 RB1 OSC2 XTAL1 RB2 XTAL2
X1
RS1*
X2
RS2*
C1
1-16MHz
C2
C3
32.768kHz
C4
*RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer's data. See Chapter 16 for component value requirements.
Figure 5-1. Oscillator External Connections The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer's data for more information.
5.3 I/O Signals
The following paragraphs describe the oscillator I/O signals.
5.3.1 Crystal Amplifier Input Pin (OSC1, XTAL1)
OSC1 and XTAL1 pin are input to the crystal oscillator amplifier. Schmitt trigger and glitch filter are implemented on this pin in order to improve the EMC performance. See Chapter 16 Electrical Specifications for detail specification of the glitch filter.
5.3.2 Crystal Amplifier Output Pin (OSC2 & XTAL2)
OSC2 or XTAL2 pin is the output of the crystal oscillator inverting amplifier.
5.3.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal from the system integration module (SIM) enables/disables the x-tal oscillator circuit.
MC68HC08LT8 Data Sheet, Rev. 1 52 Freescale Semiconductor
Low Power Modes
5.4 Low Power Modes
The WAIT and STOP instructions put the MCU in low power consumption standby mode.
5.4.1 Wait Mode
The WAIT instruction has no effect on the oscillator module.
5.4.2 Stop Mode
If STOP_XCLKEN = 1 CGMXCLK will keep on running during STOP mode else CGMXCLK will be stopped during STOP mode. If STOP_XTALEN = 1 32KXCLK will keep on running during STOP mode else 32KXCLK will be stopped during STOP mode.
5.5 Oscillator During Break Mode
The oscillator will continue to drive CGMXCLK when the device enters the break state.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 53
Oscillator (OSC)
MC68HC08LT8 Data Sheet, Rev. 1 54 Freescale Semiconductor
Chapter 6 Timer Interface Module (TIM)
6.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with Input capture, output compare, and pulse-width-modulation functions. Figure 6-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
6.2 Features
Features of the TIM include: * Two input capture/output compare channels: - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * Buffered and unbuffered pulse-width-modulation (PWM) signal generation * Programmable TIM clock input with 7-frequency internal bus clock prescaler selection * Free-running or modulo up-count operation * Toggle any channel pin on overflow * TIM counter stop and reset bits
6.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where "1" is used to indicate TIM1 and "2" is used to indicate TIM2. The two TIMs share four I/O pins with four I/O port pins. The full names of the TIM I/O pins are listed in Table 6-1. The generic pin names appear in the text that follows. Table 6-1. Pin Name Conventions
TIM Generic Pin Names: Full TIM Pin Names: TIM1 TIM2 T[1,2]CH0 PTB2/T1CH0/PPIECK PTB0/T2CH0 T[1,2]CH1 PTB3/T1CH1 PTB1/T2CH1
NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 55
Timer Interface Module (TIM)
6.4 Functional Description
Figure 6-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels.
PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS0A CH1F CH01IE CH1IE INTERRUPT LOGIC ELS0B ELS0A CH1MAX PORT LOGIC T[1,2]CH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC T[1,2]CH0 PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
Figure 6-1. TIM Block Diagram Figure 6-2 summarizes the timer registers. NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC.
MC68HC08LT8 Data Sheet, Rev. 1 56 Freescale Semiconductor
Functional Description Addr. $0020 Register Name Bit 7 TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 6 TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 14 5 TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 13 4 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 12 3 0 0 11 0 3 0 11 1 3 1 ELS0B 0 11 2 PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 10 1 PS1 0 9 0 1 0 9 1 1 1 TOV0 0 9 Bit 0 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
TIM1 Status and Control Register (T1SC) TIM1 Counter Register High (T1CNTH) TIM1 Counter Register Low (T1CNTL) TIM Counter Modulo Register High (TMODH) TIM1 Counter Modulo Register Low (T1MODL) TIM1 Channel 0 Status and Control Register (T1SC0) TIM1 Channel 0 Register High (T1CH0H) TIM1 Channel 0 Register Low (T1CH0L) TIM1 Channel 1 Status and Control Register (T1SC1) TIM1 Channel 1 Register High (T1CH1H) TIM1 Channel 1 Register Low (T1CH1L) TIM2 Status and Control Register (T2SC) TIM2 Counter Register High (T2CNTH) TIM2 Counter Register Low (T2CNTL) TIM2 Counter Modulo Register High (T2MODH)
Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1
TOIE 0 14 0 6 0 14
TSTOP 1 13 0 5 0 13
Indeterminate after reset 0 0 TRST 0 0 12 11 0 4 0 12 1 0 3 0 11 1
PS2 0 10 0 2 0 10 1
PS1 0 9 0 1 0 9 1
PS0 0 Bit 8 0 Bit 0 0 Bit 8 1
1 1 = Unimplemented
Figure 6-2. TIM I/O Register Summary (Sheet 1 of 2)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 57
Timer Interface Module (TIM) Addr. $002F Register Name Bit 7 Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 1 CH0F 0 0 Bit 15 6 6 1 CH0IE 0 14 5 5 1 MS0B 0 13 4 4 1 MS0A 0 12 3 3 1 ELS0B 0 11 2 2 1 ELS0A 0 10 1 1 1 TOV0 0 9 Bit 0 Bit 0 1 CH0MAX 0 Bit 8
$0030
$0031
$0032
$0033
$0034
$0035
TIM2 Counter Modulo Register Low (T2MODL) TIM2 Channel 0 Status and Control Register (T2SC0) TIM2 Channel 0 Register High (T2CH0H) TIM2 Channel 0 Register Low (T2CH0L) TIM2 Channel 1 Status and Control Register (T2SC1) TIM2 Channel 1 Register High (T2CH1H) TIM2 Channel 1 Register Low (T2CH1L)
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
Indeterminate after reset = Unimplemented
Figure 6-2. TIM I/O Register Summary (Sheet 2 of 2) 6.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source.
6.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
6.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 6.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 6.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers.
MC68HC08LT8 Data Sheet, Rev. 1 58 Freescale Semiconductor
Functional Description
An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. * When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 6.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
6.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 6-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 59
Timer Interface Module (TIM)
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 6.9.1 TIM Status and Control Register.
OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE WIDTH TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 6-3. PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 6.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 6.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. * When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
MC68HC08LT8 Data Sheet, Rev. 1 60 Freescale Semiconductor
Functional Description
6.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 6.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 6-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 6-3.) NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 61
Timer Interface Module (TIM)
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 6.9.4 TIM Channel Status and Control Registers.)
6.5 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. * TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
6.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
6.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
6.7 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 21.5.4 SIM Break Flag Control Register.)
MC68HC08LT8 Data Sheet, Rev. 1 62 Freescale Semiconductor
I/O Signals
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
6.8 I/O Signals
Port B shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and T2CH1 as described in 6.3 Pin Name Conventions. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
6.9 I/O Registers
NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC. These I/O registers control and monitor operation of the TIM: * TIM status and control register (TSC) * TIM counter registers (TCNTH:TCNTL) * TIM counter modulo registers (TMODH:TMODL) * TIM channel status and control registers (TSC0, TSC1) * TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
6.9.1 TIM Status and Control Register
The TIM status and control register (TSC): * Enables TIM overflow interrupts * Flags TIM overflows * Stops the TIM counter * Resets the TIM counter * Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: Write: Reset: TOF 0 0 6 TOIE 0 5 TSTOP 1 4 0 TRST 0 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0
= Unimplemented
Figure 6-4. TIM Status and Control Register (TSC)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 63
Timer Interface Module (TIM)
TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 6-2 shows. Reset clears the PS[2:0] bits. Table 6-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 Not available
MC68HC08LT8 Data Sheet, Rev. 1 64 Freescale Semiconductor
I/O Registers
6.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Figure 6-5. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Figure 6-6. TIM Counter Registers Low (TCNTL)
6.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T2MODH, $002E Bit 7 Read: Write: Reset: Bit 15 1 6 14 1 5 13 1 4 12 1 3 11 1 2 10 1 1 9 1 Bit 0 Bit 8 1
Figure 6-7. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F Bit 7 Read: Write: Reset: Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1
Figure 6-8. TIM Counter Modulo Register Low (TMODL) NOTE Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 65
Timer Interface Module (TIM)
6.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers: * Flags input captures and output compares * Enables input capture and output compare interrupts * Selects input capture, output compare, or PWM operation * Selects high, low, or toggling output on output compare * Selects rising edge, falling edge, or any edge as the active input capture trigger * Selects output toggling on TIM overflow * Selects 0% and 100% PWM duty cycle * Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030 Bit 7 Read: Write: Reset: CH0F 0 0 6 CH0IE 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
Figure 6-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033 Bit 7 Read: Write: Reset: CH1F 0 0 6 CH1IE 0 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0
Figure 6-10. TIM Channel 1 Status and Control Register (TSC1) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers.
MC68HC08LT8 Data Sheet, Rev. 1 66 Freescale Semiconductor
I/O Registers
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 6-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See Table 6-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 6-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 6-3. Mode, Edge, and Level Selection
MSxB:MSxA X0 X1 00 00 00 01 01 01 1X 1X 1X ELSxB:ELSxA 00 Output preset 00 01 10 11 01 10 11 01 10 11 Buffered output compare or buffered PWM Output compare or PWM Input capture Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare Mode Configuration Pin under port control; initial output level high
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 67
Timer Interface Module (TIM)
NOTE Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx -- Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow NOTE When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 6-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 6-11. CHxMAX Latency
6.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
MC68HC08LT8 Data Sheet, Rev. 1 68 Freescale Semiconductor
I/O Registers
Address: T1CH0H, $0026 and T2CH0H, $0031 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Indeterminate after reset
Figure 6-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032 Bit 7 Read: Write: Reset: Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Indeterminate after reset
Figure 6-13. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0034 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Indeterminate after reset
Figure 6-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035 Bit 7 Read: Write: Reset: Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Indeterminate after reset
Figure 6-15. TIM Channel 1 Register Low (TCH1L)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 69
Timer Interface Module (TIM)
MC68HC08LT8 Data Sheet, Rev. 1 70 Freescale Semiconductor
Chapter 7 Programmable Periodic Interrupt (PPI)
7.1 Introduction
This section describes the programmable periodic interrupt (PPI) module. The PPI will generate periodic interrupts at user selectable rates using a counter clocked by the selected clock.
7.2 Features
Features of the PPI include: * Seven user selectable periodic interrupts * User selectable clock source: - 32kHz (32KXCLK) clock from crystal oscillator - External clock from PPIECK pin
7.3 Functional Description
The PPI module generates periodic interrupt requests to the CPU. When PPI counter reaches the defined count, it generates an interrupt request. The latched status of interrupt generation of the PPI can be read directly from the PPI1L bit. The PPI counter can count and generate interrupts even when the MCU is in stop mode if the corresponding clock source is enabled. Figure 7-1 is a block diagram of the PPI.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 71
Programmable Periodic Interrupt (PPI)
PPI1CLKS[1:0] SEL PPIECK 32KXCLK OE VDD D OV E CLR SEL R SYNCHRONIZER Q PPI1L
COUNTER CLK
ONE SHOT
PPI1MSK
PPI1 INTERRUPT REQUEST
RST
RESET PPI1L VECTOR FETCH DECODER PPI1IE2 PPI1IE1 PPI1IE0
INTERNAL ADDRESS BUS
Figure 7-1. Programmable Periodic Interrupt Block Diagram
7.4 I/O Pins
The external clock input option of the PPI is from the PPIECK pin and is selected by the clock select bits, PPI1CLKS[1:0]. The maximum PPIECK frequency is four times the bus frequency.
7.5 Low-Power Modes
The PPI module remains active (crystal clock source is not affected if crystal clock is enabled in stop mode; counter can count and can generate interrupts) in wait and stop mode if proper clocking source is supplied.
MC68HC08LT8 Data Sheet, Rev. 1 72 Freescale Semiconductor
PPI1 Status and Control Register (PPI1SCR)
7.6 PPI1 Status and Control Register (PPI1SCR)
The PPI1 status and control register (PPI1SCR) controls and monitors the operation of the PPI module.
Address: Read: Write: Reset: $0019 Bit 7 PPI1L 0 6 PPI1MSK 0 5 PPICLKS1 1 4
PPI1CLKS0
3 0 0
2 PPI1IE2 0
1 PPI1IE1 0
Bit 0 PPI1IE0 0
0
Figure 7-2. PPI1 Status and Control Register (PPI1SCR) PPI1L -- PPI1 Interrupt Flag This read/write bit indicates a interrupt request is generated by PPI1 and is pending for acknowledgement. This bit generates an interrupt to the CPU if PPI1MSK=0. The PPI1L bit is cleared by writing logic 1 to it. 1 = Read: PPI1 interrupt request is pending / Write: PPI1 interrupt acknowledge 0 = No PPI1 interrupt request is pending PPI1MSK -- PPI1 Interrupt Mask Writing a logic one to this read/write bit disables PPI1 interrupt requests. Reset clears PPI1MSK. 1 = PPI1 interrupt requests disabled 0 = PPI1 interrupt requests enabled PPI1CLKS[1:0] -- PPI1 Clock Source Select Bits These two bits select the clock source for the PPI. Table 7-1. PPI1 Clock Source Selection
PPI1CLKS[1:0] 00 01 10 11 Clock Source for PPI1 Reserved External clock from PPIECK pin 32KXCLK from OSC module Reserved
PPI1IE[2:0] --PPI1 Interrupt Period Select Bits These three bits select the PPI interrupt period. The PPI is disabled when PPI1IE[2:0] are zero and no interrupts are generated. Table 7-2. PPI1 Interrupt Period Selection
PPI1IE[2:0] 000 001 010 011 100 101 110 111 Interrupt Period PPI and its associated interrupts are disabled 512 PPI counts 1,024 PPI counts 2,048 PPI counts 4,096 PPI counts 8,192 PPI counts 16,384 PPI counts 32,768 PPI counts
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 73
Programmable Periodic Interrupt (PPI)
MC68HC08LT8 Data Sheet, Rev. 1 74 Freescale Semiconductor
Chapter 8 Liquid Crystal Display (LCD) Driver
8.1 Introduction
This section describes the liquid crystal display (LCD) driver module. The LCD driver module can drive a maximum of 25 frontplanes and 4 backplanes, depending on the LCD duty selected.
8.2 Features
Features of the LCD driver module include the following: * Software programmable driver segment configurations: - 24 frontplanes x 4 backplanes (96 segments) - 25 frontplanes x 3 backplanes (75 segments) - 25 frontplanes x 1 backplane (25 segments) * LCD bias voltages generated by internal resistor ladder * Software programmable contrast control
8.3 Pin Name Conventions and I/O Register Addresses
Three dedicated I/O pins are for the backplanes, BP0-BP2; twenty four frontplanes, FP1-FP24, are shared with port B, C, D, and E pins. FP0 and BP3 shares the same pin and configured by the DUTY[1:0] bits in the LCD clock register. The full names of the LCD output pins are shown in Table 8-1. The generic pin names appear in the text that follows. Table 8-1. Pin Name Conventions
LCD Generic Pin Name FP0/BP3 BP0-BP2 FP1-FP2 FP3-FP10 FP11-FP18 FP19-FP24 Full MCU Pin Name FP0/BP3 BP0-BP2 PTB6/FP1-PTB7/FP2 PTE0/FP3-PTE7/FP10 PTD0/FP11-PTD7/FP18 PTC0/FP19-PTC5/FP24 Pin Selected for LCD Function by: -- -- LCDE in LCDCR PEE in CONFIG2 LCDE in LCDCR PDE in CONFIG2 LCDE in LCDCR PCEL:PCEH in CONFIG2 LCDE in LCDCR
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 75
Liquid Crystal Display (LCD) Driver Addr. $004F Register Name LCD Clock Register (LCDCLK) LCD Control Register (LCDCR) LCD Data Register 1 (LDAT1) LCD Data Register 2 (LDAT2) LCD Data Register 3 (LDAT3) LCD Data Register 4 (LDAT4) LCD Data Register 5 (LDAT5) LCD Data Register 6 (LDAT6) LCD Data Register 7 (LDAT7) LCD Data Register 8 (LDAT8) LCD Data Register 9 (LDAT9) LCD Data Register 10 (LDAT10) LCD Data Register 11 (LDAT11) LCD Data Register 12 (LDAT12) LCD Data Register 13 (LDAT13) Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Bit 7 0 0 LCDE 0 F1B3 U F3B3 U F5B3 U F7B3 U F9B3 U F11B3 U F13B3 U F15B3 U F17B3 U F19B3 U F21B3 U F23B3 U 0 0 U = Unaffected 6 FCCTL1 0 0 0 F1B2 U F3B2 U F5B2 U F7B2 U F9B2 U F11B2 U F13B2 U F15B2 U F17B2 U F19B2 U F21B2 U F23B2 U 0 0 5 FCCTL0 0 FC 0 F1B1 U F3B1 U F5B1 U F7B1 U F9B1 U F11B1 U F13B1 U F15B1 U F17B1 U F19B1 U F21B1 U F23B1 U 0 0 4 DUTY1 0 LC 0 F1B0 U F3B0 U F5B0 U F7B0 U F9B0 U F11B0 U F13B0 U F15B0 U F17B0 U F19B0 U F21B0 U F23B0 U 0 3 DUTY0 0 LCCON3 0 F0B3 U F2B3 U F4B3 U F6B3 U F8B3 U F10B3 U F12B3 U F14B3 U F16B3 U F18B3 U F20B3 U F22B3 U F24B3 2 LCLK2 0 LCCON2 0 F0B2 U F2B2 U F4B2 U F6B2 U F8B2 U F10B2 U F12B2 U F14B2 U F16B2 U F18B2 U F20B2 U F22B2 U F24B2 U 1 LCLK1 0 LCCON1 0 F0B1 U F2B1 U F4B1 U F6B1 U F8B1 U F10B1 U F12B1 U F14B1 U F16B1 U F18B1 U F20B1 U F22B1 U F24B1 U Bit 0 LCLK0 0 LCCON0 0 F0B0 U F2B0 U F4B0 U F6B0 U F8B0 U F10B0 U F12B0 U F14B0 U F16B0 U F18B0 U F20B0 U F22B0 U F24B0 U
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
$005A
$005B
$005C
$005D
$005E
0 U = Unimplemented
Figure 8-1. LCD I/O Register Summary
MC68HC08LT8 Data Sheet, Rev. 1 76 Freescale Semiconductor
Functional Description
8.4 Functional Description
Figure 8-2 shows a block diagram of the LCD driver module, and Figure 8-3 shows a simplified schematic of the LCD system. The LCD driver module uses a 1/3 biasing method. The LCD power is supplied by the VLCD pin. Voltages VLCD1, VLCD2, and VLCD3 are generated by an internal resistor ladder. The LCD data registers, LDAT1-LDAT13, control the LCD segments' ON/OFF, with each data register controlling two frontplanes. When a logic 1 is written to a FxBx bit in the data register, the corresponding frontplane-backplane segment will turn ON. When a logic 0 is written, the segment will turn OFF. When the LCD driver module is disabled (LCDE = 0), the LCD display will be OFF, all backplane and frontplane drivers have the same potential as VDD. The resistor ladder is disconnected from VDD to reduce power consumption.
PTD0/FP11
PTD1/FP12
PTD2/FP13
PTD3/FP14
PTD4/FP15
PTD5/FP16
PTD6/FP17
PORT-E LOGIC PORT-B LOGIC
PORT-D LOGIC
LCD FRONTPLANE DRIVER AND DATA LATCH
PTC0/FP19 PTC1/FP20
PTB7/FP2 PTB6/FP1
PORT-C LOGIC
PTD7/FP18
PTE7/FP10
PTE0/FP3
PTE1/FP4
PTE2/FP5
PTE3/FP6
PTE4/FP7
PTE5/FP8
PTE6/FP9
PTC2/FP21 PTC3/FP22 PTC4/FP23 PTC5/FP24
FP0/BP3 BP2 BP1 BP0
1/3 1/4
LCDE (LCDCR) DRIVER STATE CONTROL
1/1 1/3 1/4
BACKPLANE
Figure 8-2. LCD Block Diagram
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 77
INTERNAL BUS
Liquid Crystal Display (LCD) Driver
LCD
FP0
FP1
FP24
BP0
BP1
BP2
RFP VLCD VLCD RLCD RLCD RLCD VLCD1 VLCD2 VLCD3 Vbias VR BIAS CONTROL
RFP
RFP
RBP
RBP
RBP
LCCON[3:0]
Figure 8-3. Simplified LCD Schematic (1/3 Duty, 1/3 Bias)
8.4.1 LCD Duty
The setting of the LCD output waveform duty is dependent on the number of backplane drivers required. Three LCD duties are available: * Static duty -- BP0 is used only * 1/3 duty -- BP0, BP1, and BP3 are used * 1/4 duty -- BP0, BP1, BP2, and BP3 are used When the LCD driver module is enabled the backplane waveforms for the selected duty are driven out of the backplane pins. The backplane waveforms are periodic and are shown are shown in Figure 8-5, Figure 8-6, and Figure 8-7.
MC68HC08LT8 Data Sheet, Rev. 1 78 Freescale Semiconductor
Functional Description
8.4.2 LCD Voltages (VLCD, VLCD1, VLCD2, VLCD3)
The voltage VLCD is from the VLCD pin and must not exceed VDD. VLCD1, VLCD2, and VLCD3 are internal bias voltages for the LCD driver waveforms. They are derived from VLCD using a resistor ladder (see Figure 8-3). The relative potential of the LCD voltages are: * VLCD = VDD * VLCD1 = 2/3 x (VLCD - Vbias) * VLCD2 = 1/3 x (VLCD - Vbias) * VLCD3 = Vbias The VLCD3 bias voltage, Vbias, is controlled by the LCD contrast control bits, LCCON[2:0].
8.4.3 LCD Cycle Frame
The LCD driver module uses the 32KXCLK (see Chapter 5 Oscillator (OSC)) as the input reference clock. This clock is divided to produce the LCD waveform base clock, LCDCLK, by configuring the LCLK[2:0] bits in the LCD clock register. The LCDCLK clocks the backplane and the frontplane output waveforms. The LCD cycle frame is determined by the equation:
1 LCD WAVEFORM BASE CLOCK x DUTY
LCD CYCLE FRAME =
For example, for 1/3 duty and 256Hz waveform base clock:
LCD CYCLE FRAME = 1 256 x (1/3)
= 11.72 ms
8.4.4 Fast Charge and Low Current
The default value for each of the bias resistors (see Figure 8-3), RLCD, in the resistor ladder is approximately 37k at VLCD = 3V. The relatively high current drain through the 37k resistor ladder may not be suitable for some LCD panel connections. Lowering this current is possible by setting the LC bit in the LCD control register, switching the RLCD value to 146k. Although the lower current drain is desirable, but in some LCD panel connections, the higher current is required to drive the capacitive load of the LCD panel. In most cases, the higher current is only required when the LCD waveforms change state (the rising and falling edges in the LCD output waveforms). The fast charge option is designed to have the high current for the switching and the low current for the steady state. Setting the FC bit in the LCD control register selects the fast charge option. The RLCD value is set to 37k (for high current) for a fraction of time for each LCD waveform switching edge, and then back to 146k for the steady state period. The duration of the fast charge time is set by configuring the FCCTL[1:0] bits in the LCD clock register, and can be LCDCLK/32, LCDCLK/64, or LCDCLK/128. Figure 8-4 shows the fast charge clock relative to the BP0 waveform.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 79
Liquid Crystal Display (LCD) Driver
LCDCLK
LCD WAVEFORM EXAMPLE: BP0
FAST CHARGE CLOCK HIGH CURRENT SELECTED BEFORE SWITCHING EDGE, PERIOD IS DEFINED BY FCCTL[1:0]
Figure 8-4. Fast Charge Timing
8.4.5 Contrast Control
The contrast of the connected LCD panel can be adjusted by configuring the LCCON[3:0] bits in the LCD control register. The LCCON[3:0] bits provide a 16-step contrast control, which adjusts the bias voltage in the resistor ladder for LCD voltage, VLCD3. The relative voltages, VLCD1 and VLCD2, are altered accordingly. For example, setting LCCON[3:0] = $F, the relative panel potential voltage (VLCD - VLCD3) is reduced from maximum 3.3V to approximate 2.45V.
8.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The LCD driver module continues normal operation in wait mode. If the LCD is not required in wait mode, power down the LCD module by clearing the LCDE bit before executing the WAIT instruction.
8.5.2 Stop Mode
For continuous LCD module operation in stop mode, the oscillator stop mode enable bit (STOP_XTALEN in CONFIG2 register) must be set before executing the STOP instruction. When STOP_XTALEN is set, 32KXCLK continues to drive the LCD module. If STOP_XTALEN bit is cleared, the LCD module is inactive after the execution of a STOP instruction. The STOP instruction does not affect LCD register states. LCD module operation resumes after an external interrupt. To further reduce power consumption, the LCD module should be powered-down by clearing the LCDE bit before executing the STOP instruction.
MC68HC08LT8 Data Sheet, Rev. 1 80 Freescale Semiconductor
I/O Signals
8.6 I/O Signals
The LCD driver module has twenty-eight (28) output pins. * FP0/BP3 (multiplexed; selected as FP0 or BP3 by DUTY[1:0]) * BP0-BP2 * FP1-FP2 (shared with port B) * FP3-FP10 (shared with port E) * FP11-FP18 (shared with port D) * FP19-FP24 (shared with port C)
8.6.1 BP0-BP3 (Backplane Drivers)
BP0-BP3 are the backplane driver output pins. These are connected to the backplane of the LCD panel. Depending on the LCD duty selected, the voltage waveforms in Figure 8-5, Figure 8-6, and Figure 8-7 appear on the backplane pins. BP3 pin is only used when 1/4 duty is selected. The pin becomes FP0 for static and 1/3 duty operations.
DUTY = STATIC 1FRAME VLCD VLCD1 VLCD2 VLCD3 NOTES: 1. BP1, BP2, and BP3 are not used. 2. At static duty, 1FRAME is equal to the cycle of LCD waveform base clock.
BP0
Figure 8-5. Static LCD Backplane Driver Waveform
DUTY = 1/3 1FRAME VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3
BP0
BP1
BP2
NOTES: 1. BP3 is not used. 2. At 1/3 duty, 1FRAME has three times the cycle of LCD waveform base clock.
Figure 8-6. 1/3 Duty LCD Backplane Driver Waveforms
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 81
Liquid Crystal Display (LCD) Driver
DUTY = 1/4
1FRAME VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3
BP0
BP1
BP2
BP3
Figure 8-7. 1/4 Duty LCD Backplane Driver Waveforms
8.6.2 FP0-FP24 (Frontplane Drivers)
FP0-FP24 are the frontplane driver output pins. These are connected to the frontplane of the LCD panel. Depending on LCD duty selected and the contents in the LCD data registers, the voltage waveforms in Figure 8-8, Figure 8-9, Figure 8-10 and Figure 8-11 appear on the frontplane pins.
DUTY = STATIC DATA LATCH: 1 = ON, 0 = OFF FxB0 -- -- -- 0 1FRAME VLCD VLCD1 VLCD2 VLCD3 FxB0 -- -- -- 1 VLCD VLCD1 VLCD2 VLCD3 FPx OUTPUT
Figure 8-8. Static LCD Frontplane Driver Waveforms
MC68HC08LT8 Data Sheet, Rev. 1 82 Freescale Semiconductor
I/O Signals
DUTY = 1/3 DATA LATCH: 1 = ON, 0 = OFF 1FRAME FxB2 -- 0 FxB1 0 FxB0 0 VLCD VLCD1 VLCD2 VLCD3 FxB2 -- 0 FxB1 0 FxB0 1 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 FPx OUTPUT
FxB2 -- 0
FxB1 1
FxB0 0
FxB2 -- 1
FxB1 0
FxB0 0
FxB2 -- 0
FxB1 1
FxB0 1
FxB2 -- 1
FxB1 1
FxB0 0
FxB2 -- 1
FxB1 0
FxB0 1
FxB2 -- 1
FxB1 1
FxB0 1
Figure 8-9. 1/3 Duty LCD Frontplane Driver Waveforms
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 83
Liquid Crystal Display (LCD) Driver
DUTY = 1/4 DATA LATCH: 1 = ON, 0 = OFF FxB3 0 FxB2 0 FxB1 0 FxB0 0
FPx OUTPUT 1FRAME VLCD VLCD1 VLCD2 VLCD3
FxB3 0
FxB2 0
FxB1 0
FxB0 1
FxB3 0
FxB2 0
FxB1 1
FxB0 0
FxB3 0
FxB2 0
FxB1 1
FxB0 1
FxB3 0
FxB2 1
FxB1 0
FxB0 0
FxB3 0
FxB2 1
FxB1 0
FxB0 1
FxB3 0
FxB2 1
FxB1 1
FxB0 0
FxB3 0
FxB2 1
FxB1 1
FxB0 1
Figure 8-10. 1/4 Duty LCD Frontplane Driver Waveforms
MC68HC08LT8 Data Sheet, Rev. 1 84 Freescale Semiconductor
I/O Signals
DUTY = 1/4 DATA LATCH: 1 = ON, 0 = OFF FxB3 1 FxB2 0 FxB1 0 FxB0 0
FPx OUTPUT 1FRAME VLCD VLCD1 VLCD2 VLCD3
FxB3 1
FxB2 0
FxB1 0
FxB0 1
FxB3 1
FxB2 0
FxB1 1
FxB0 0
FxB3 1
FxB2 0
FxB1 1
FxB0 1
FxB3 1
FxB2 1
FxB1 0
FxB0 0
FxB3 1
FxB2 1
FxB1 0
FxB0 1
FxB3 1
FxB2 1
FxB1 1
FxB0 0
FxB3 1
FxB2 1
FxB1 1
FxB0 1
Figure 8-11. 1/4 Duty LCD Frontplane Driver Waveforms (continued)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 85
Liquid Crystal Display (LCD) Driver
8.7 Seven Segment Display Connection
The following shows an example for connecting a 7-segment LCD display to the LCD driver. The example uses 1/3 duty cycle, with pins BP0, BP1, BP2, FP0, FP1, and FP2 connected as shown in Figure 8-12. The output waveforms are shown in Figure 8-13.
FP CONNECTION a f b f BP CONNECTION a BP0 (a, b COMMONED)
g
g
b
e
d
c
e
d
c
BP1 (c, f, g COMMONED) BP2 (d, e COMMONED)
FP2 (b, c COMMONED) FP1 (a, d, g COMMONED) FP0 (e, f COMMONED) The segment assignments for each bit in the data registers are:
F1B3 LDAT1 $0052 F1B2 F1B1 F1B0 F0B3 F0B2 F0B1 F0B0
--
d FP1
g
a
--
e FP0
f
--
F3B3 LDAT2 $0053
F3B2
F3B1
F3B0
F2B3
F2B2
F2B1
F2B0
--
--
--
--
--
-- FP2
c
b
To display the character "4": LDAT1 = X010X01X, LDAT2 = XXXXXX11
a LDAT1 $0052
X
0
1
0
X
0
1
X
f e
g d
b c
LDAT2 $0053
X
X
X
X
X
X
1
1
X = don't care
Figure 8-12. 7-Segment Display Example
MC68HC08LT8 Data Sheet, Rev. 1 86 Freescale Semiconductor
Seven Segment Display Connection
DUTY = 1/3
1FRAME VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3 VLCD VLCD1 VLCD2 VLCD3
BP0
BP1
BP2
F0B2 -- 0
F0B1 1
F0B0 0 FP0
F1B2 -- 0
F1B1 1
F1B0 0 FP1
F2B2 -- 0
F2B1 1
F2B0 1 FP2
Figure 8-13. BP0-BP2 and FP0-FP2 Output Waveforms for 7-Segment Display Example The voltage waveform across the "f" segment of the LCD (between BP1 and FP0) is illustrated in Figure 8-14. As shown in the waveform, the voltage peaks reach the LCD-ON voltage, VLCD, therefore, the segment will be ON.
+VLCD +VLCD1 +VLCD2 BP1-FP0 0 -VLCD2 -VLCD1 -VLCD
Figure 8-14. "f" Segment Voltage Waveform
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 87
Liquid Crystal Display (LCD) Driver
The voltage waveform across the "e" segment of the LCD (between BP2 and FP0) is illustrated in Figure 8-15. As shown in the waveform, the voltage peaks do not reach the LCD-ON voltage, VLCD, therefore, the segment will be OFF.
+VLCD +VLCD1 +VLCD2 0 -VLCD2 -VLCD1 -VLCD
BP2-FP0
Figure 8-15. "e" Segment Voltage Waveform
8.8 I/O Registers
Fifteen (15) registers control LCD driver module operation: * LCD control register (LCDCR) * LCD clock register (LCDCLK) * LCD data registers (LDAT1-LDAT13)
8.8.1 LCD Control Register (LCDCR)
The LCD control register (LCDCR): * Enables the LCD driver module * Selects bias resistor value and fast-charge control * Selects LCD contrast
Address: Read: Write: Reset: $0051 Bit 7 LCDE 0 6 0 0 5 FC 0 4 LC 0 3 LCCON3 0 2 LCCON2 0 1 LCCON1 0 Bit 0 LCCON0 0
= Unimplemented
Figure 8-16. LCD Control Register (LCDCR) LCDE -- LCD Enable This read/write bit enables the LCD driver module; the backplane and frontplane drive LCD waveforms out of BPx and FPx pins. Reset clears the LCDE bit. 1 = LCD driver module enabled 0 = LCD driver module disabled FC -- Fast Charge LC -- Low Current These read/write bits are used to select the value of the resistors in resistor ladder for LCD voltages. Reset clears the FC and LC bits.
MC68HC08LT8 Data Sheet, Rev. 1 88 Freescale Semiconductor
I/O Registers
Table 8-2. Resistor Ladder Selection
FC X 0 1 LC 0 1 1 Action Each resistor is approximately 37 k (default) Each resistor is approximately 146 k Fast charge mode
LCCON[3:0] -- LCD Contrast Control These read/write bits select the bias voltage, Vbias. This voltage controls the contrast of the LCD. Maximum contrast is set when LCCON[3:0] =%0000; minimum contrast is set when LCCON[3:0] =%1111. Table 8-3. LCD Bias Voltage Control
LCCON3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LCCON2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LCCON1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LCCON0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bias Voltage (approximate % of VDD) 0.6 2.9 5.2 7.4 9.6 11.6 13.5 15.3 17.2 18.8 20.5 22.0 23.6 25.0 26.4 27.7
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 89
Liquid Crystal Display (LCD) Driver
8.8.2 LCD Clock Register (LCDCLK)
The LCD clock register (LCDCLK): * Selects the fast charge duty cycle * Selects LCD driver duty cycle * Selects LCD waveform base clock
Address: Read: Write: Reset: 0 $004F Bit 7 0 6 FCCTL1 0 5 FCCTL0 0 4 DUTY1 0 3 DUTY0 0 2 LCLK2 0 1 LCLK1 0 Bit 0 LCLK0 0
= Unimplemented
Figure 8-17. LCD Clock Register (LCDCLK) FCCTL[1:0] -- Fast Charge Duty Cycle Select These read/write bits select the duty cycle of the fast charge duration. Reset clears these bits. (See 8.4.4 Fast Charge and Low Current) Table 8-4. Fast Charge Duty Cycle Selection
FCCTL1:FCCTL0 00 01 10 11 Fast Charge Duty Cycle In each LCDCLK/2 period, each bias resistor is reduced to 37 k for a duration of LCDCLK/32. In each LCDCLK/2 period, each bias resistor is reduced to 37 k for a duration of LCDCLK/64. In each LCDCLK/2 period, each bias resistor is reduced to 37 k for a duration of LCDCLK/128. Not used
DUTY[1:0] -- Duty Cycle Select These read/write bits select the duty cycle of the LCD driver output waveforms. The multiplexed FP0/BP3 pin is controlled by the duty cycle selected. Reset clears these bits. Table 8-5. LCD Duty Cycle Selection
DUTY1:DUTY0 00 01 10 11 Description Static selected; FP0/BP3 pin function as FP0. 1/3 duty cycle selected; FP0/BP3 pin functions as FP0. 1/4 duty cycle selected; FP0/BP3 pin functions as BP3. Not used
LCLK[2:0] -- LCD Waveform Base Clock Select These read/write bits selects the LCD waveform base clock. Reset clears these bits.
MC68HC08LT8 Data Sheet, Rev. 1 90 Freescale Semiconductor
I/O Registers
Table 8-6. LCD Waveform Base Clock Selection
Divide Ratio 128 256 512 1024 LCD Waveform Base Clock Frequency LCDCLK (Hz) fXTAL = 32.768kHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 256 128 64 32 Reserved Reserved Reserved Reserved LCD Frame Rate fXTAL = 32.768kHz 1/3 duty 85.3 42.7 21.3 10.7 1/4 duty 64 32 16 8
LCLK2
LCLK1
LCLK0
8.8.3 LCD Data Registers (LDAT1-LDAT17)
The thirteen (13) LCD data registers enable and disable the drive to the corresponding LCD segments.
Addr. $0052
Register Name LCD Data Register 1 (LDAT1) LCD Data Register 2 (LDAT2) LCD Data Register 3 (LDAT3) LCD Data Register 4 (LDAT4) LCD Data Register 5 (LDAT5) LCD Data Register 6 (LDAT6) LCD Data Register 7 (LDAT7) Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset:
Bit 7 F1B3 U F3B3 U F5B3 U F7B3 U F9B3 U F11B3 U F13B3 U U = Unaffected
6 F1B2 U F3B2 U F5B2 U F7B2 U F9B2 U F11B2 U F13B2 U
5 F1B1 U F3B1 U F5B1 U F7B1 U F9B1 U F11B1 U F13B1 U
4 F1B0 U F3B0 U F5B0 U F7B0 U F9B0 U F11B0 U F13B0
3 F0B3 U F2B3 U F4B3 U F6B3 U F8B3 U F10B3 U F12B3
2 F0B2 U F2B2 U F4B2 U F6B2 U F8B2 U F10B2 U F12B2 U
1 F0B1 U F2B1 U F4B1 U F6B1 U F8B1 U F10B1 U F12B1 U
Bit 0 F0B0 U F2B0 U F4B0 U F6B0 U F8B0 U F10B0 U F12B0 U
$0053
$0054
$0055
$0056
$0057
$0058
U U = Unimplemented
Figure 8-18. LCD Data Registers 1-13 (LDAT1-LDAT13)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 91
Liquid Crystal Display (LCD) Driver Read: LCD Data Register 8 Write: (LDAT8) Reset: Read: LCD Data Register 9 Write: (LDAT9) Reset: Read: LCD Data Register 10 Write: (LDAT10) Reset: Read: LCD Data Register 11 Write: (LDAT11) Reset: Read: LCD Data Register 12 Write: (LDAT12) Reset: Read: LCD Data Register 13 Write: (LDAT13) Reset:
$0059
F15B3 U F17B3 U F19B3 U F21B3 U F23B3 U 0 0 U = Unaffected
F15B2 U F17B2 U F19B2 U F21B2 U F23B2 U 0 0
F15B1 U F17B1 U F19B1 U F21B1 U F23B1 U 0 0
F15B0 U F17B0 U F19B0 U F21B0 U F23B0 U 0
F14B3 U F16B3 U F18B3 U F20B3 U F22B3 U F24B3
F14B2 U F16B2 U F18B2 U F20B2 U F22B2 U F24B2 U
F14B1 U F16B1 U F18B1 U F20B1 U F22B1 U F24B1 U
F14B0 U F16B0 U F18B0 U F20B0 U F22B0 U F24B0 U
$005A
$005B
$005C
$005D
$005E
0 U = Unimplemented
Figure 8-18. LCD Data Registers 1-13 (LDAT1-LDAT13)
MC68HC08LT8 Data Sheet, Rev. 1 92 Freescale Semiconductor
Chapter 9 Input/Output (I/O) Ports
9.1 Introduction
Thirty-eight (38) bidirectional input-output (I/O) pins form six parallel ports. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 93
Input/Output (I/O) Ports
Addr.
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port B Data Register Write: (PTB) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: Read: Data Direction Register A Write: (DDRA) Reset: Read: Data Direction Register B Write: (DDRB) Reset: Read: Data Direction Register C Write: (DDRC) Reset: Read: Data Direction Register D Write: (DDRD) Reset: Read: Data Direction Register E Write: (DDRE) Reset: Read: Port E Data Register Write: (PTE) Reset: Read: Port-B High Current Drive Control Register Write: (HDB) Reset: U = Unaffected
Bit 7 PTA7
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
$0000
Unaffected by reset 0 PTB7 PTB6 0 PTB3 Unaffected by reset PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 PTB2 PTB1 PTB0
$0001
$0002
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA7 0 DDRB7 0 DDRC7 0 DDRD7 0 DDRE7 0 PTE7 DDRA6 0 DDRB6 0 DDRC6 0 DDRD6 0 DDRE6 0 PTE6 0 DDRC5 0 DDRD5 0 DDRE5 0 PTE5 0 DDRC4 0 DDRD4 0 DDRE4 0 PTE4 DDRA5 0 0 DDRA4 0 0 DDRB3 0 DDRC3 0 DDRD3 0 DDRE3 0 PTE3 DDRB2 0 DDRC2 0 DDRD2 0 DDRE2 0 PTE2 DDRB1 0 DDRC1 0 DDRD1 0 DDRE1 0 PTE1 DDRB0 0 DDRC0 0 DDRD0 0 DDRE0 0 PTE0 DDRA3 0 DDRA2 0 DDRA1 0 DDRA0 0
$0004
$0005
$0006
$0007
$0008
$0009
Unaffected by reset PPI1L R HDB5 0 X = Indeterminate HDB4 0 = Unimplemented HDB3 0 HDB2 0 R
PPI1CLKS1 PPI1CLKS0
$000C
0 = Reserved
0
Figure 9-1. I/O Port Register Summary
MC68HC08LT8 Data Sheet, Rev. 1 94 Freescale Semiconductor
Introduction
Table 9-1. Port Control Register Bits Summary (Sheet 1 of 2)
Module Control Port Bit 0 1 2 3 A 4 5 6 7 0 1 2 B 3 6 7 0 1 2 3 C 4 5 6 7 0 1 2 3 D 4 5 6 7 DDRD4 DDRD5 DDRD6 DDRD7 DDRB3 DDRB6 LCD DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRC7 DDRD0 DDRD1 DDRD2 DDRD3 LCD CONFIG2 ($001D) LCDCR ($0051) PDE LCDE -- -- -- -- LCD CONFIG2 ($001D) LCDCR ($0051) PCEH LCDE -- -- PCEL LCDE LCDCR ($0051) LCDE PTB7/FP2(1) PTC0/FP19 PTC1/FP20 PTC2/FP21 PTC3/FP22 PTC4/FP23(1) PTC5/FP24(1) PTC6 PTC7 PTD0/FP11 PTD1/FP12 PTD2/FP13 PTD3/FP14 PTD4/FP15 PTD5/FP16 PTD6/FP17 PTD7/FP18 DDRA4 DDRA5 -- DDRA6 DDRA7 DDRB0 TIM2 DDRB1 DDRB2 TIM1 T2SC1 ($0033) T1SC0 ($0025) HDB ($000C) T1SC1 ($0028) ELS1B:ELS1A ELS0B:ELS0A PPI1CLKS[1:0] ELS1B:ELS1A PTB1/T2CH1 PTB2/T1CH0/PPIECK PTB3/T1CH1 PTB6/FP1(1) T2SC0 ($0030) ELS0B:ELS0A -- -- PTA6 PTA7 PTB0/T2CH0 PTA4 PTA5 DDR Module DDRA0 DDRA1 KBI DDRA2 DDRA3 KBIER ($001C) KBIE2 KBIE3 PTA2/KBI2 PTA3/KBI3 Register Control Bit KBIE0 KBIE1 PTA0/KBI0 PTA1/KBI1 Pin
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 95
Input/Output (I/O) Ports
Table 9-1. Port Control Register Bits Summary (Sheet 2 of 2)
Module Control Port Bit 0 1 2 3 E 4 5 6 7 DDRE4 DDRE5 DDRE6 DDRE7 DDR Module DDRE0 DDRE1 DDRE2 DDRE3 LCD CONFIG2 ($001D) LCDCR ($0051) PEE LCDE Register Control Bit PTE0/FP3 PTE1/FP4 PTE2/FP5 PTE3/FP6 PTE4/FP7 PTE5/FP8 PTE6/FP9 PTE7/FP10 Pin
1. Pins not available on 44-pin package.
9.2 Port A
Port A is an 8-bit special function port that shares four of its port pins with the keyboard interrupt module (KBI).
9.2.1 Port A Data Register (PTA)
The port A data register contains a data latch for each of the eight port A pins.
Address: Read: Write: Reset: Alternative Function: $0000 Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by Reset KBI3 KBI2 KBI1 KBI0
Figure 9-2. Port A Data Register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBI[3:0] -- Keyboard Interrupt Channels 3 to 0 KBI[3:0] are pins used for the keyboard interrupt input. The corresponding input, KBI[3:0], can be enabled in the keyboard interrupt enable register, KBIER. Port pins used as KBI input will override any control from the port I/O logic. See Section 20. Keyboard Interrupt Module (KBI).
MC68HC08LT8 Data Sheet, Rev. 1 96 Freescale Semiconductor
Port A
9.2.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0004 Bit 7 DDRA7 0 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0
Figure 9-3. Data Direction Register A (DDRA) DDRA[7:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 9-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx
READ PTA ($0000)
Figure 9-4. Port A I/O Circuit When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 9-2 summarizes the operation of the port A pins. Table 9-2. Port A Pin Functions
DDRA Bit 0 1 Accesses to DDRA PTA Bit X(1) X I/O Pin Mode Read/Write Input, Hi-Z(2) Output DDRA[7:0] DDRA[7:0] Read Pin PTA[7:0] Write PTA[7:0](3) PTA[7:0] Accesses to PTA
1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 97
Input/Output (I/O) Ports
9.3 Port B
Port B is an 6-bit special function port that shares four of its port pins with the two timers (TIM1 and TIM2) and two of its ports pins with the liquid crystal display (LCD) driver module. Port pin, PTB2, is also shared with the external clock input of the programmable periodic interrupt (PPI) module. NOTE PTB6-PTB7 pins are not available on 44-pin package.
9.3.1 Port B Data Register (PTB)
The port B data register contains a data latch for each of the eight port B pins.
Address: $0001 Bit 7 Read: Write: Reset: Alternative Functions: Additional Functions: FP2 FP1 PTB7 6 PTB6 5 0 4 0 3 PTB3 2 PTB2 1 PTB1 Bit 0 PTB0
Unaffected by reset T1CH1 T1CH0 PPIECK High current sink T2CH1 T2CH0
Figure 9-5. Port B Data Register (PTB) PTB[7:6, 3:0] -- Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. T1CH[1:0] -- Timer 1 Channel I/O Bits The T1CH1 and T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTB2/T1CH0 and PTB3/T1CH1 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 6 Timer Interface Module (TIM). T2CH[1:0] -- Timer 2 Channel I/O Bits The T2CH1 and T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTB0/T2CH0 and PTB1/T2CH1 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 6 Timer Interface Module (TIM). PPIECK -- External Clock Source Input for PPI The PPIECK pin is the external clock input to the PPI module. It is selected by setting the bits PPI1CLKS[1:0] = 01 in the port B high current drive control register. See 7.6 PPI1 Status and Control Register (PPI1SCR). FP[2:1] -- LCD Driver Frontplanes 2-1 FP[2:1] are pins used for the frontplane output of the LCD driver module. The enable bit, LCDE, in the LCDCR register determine whether the PTB7/FP2-PTB6/FP1 pins are LCD frontplane driver pins or general-purpose I/O pins. See Chapter 8 Liquid Crystal Display (LCD) Driver.
MC68HC08LT8 Data Sheet, Rev. 1 98 Freescale Semiconductor
Port B
9.3.2 Data Direction Register B (DDRB)
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. NOTE For devices packaged in a 44-pin package, PTB6-PTB7 are not connected. DDRB6:7 should be set to a 1 to configure PTB6-PTB7 as outputs.
Address: Read: Write: Reset: $0005 Bit 7 DDRB7 0 6 DDRB6 0 5 0 0 4 0 0 3 DDRB3 0 2 DDRB2 0 1 DDRB1 0 Bit 0 DDRB0 0
Figure 9-6. Data Direction Register B (DDRB) DDRB[7:6, 3:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:6, 3:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 9-7 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBX PTBX DDRBX
READ PTB ($0001)
Figure 9-7. Port B I/O Circuit When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 9-3 summarizes the operation of the port B pins.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 99
Input/Output (I/O) Ports
Table 9-3. Port B Pin Functions
DDRB Bit 0 1 PTB Bit X
(1)
I/O Pin Mode Input, Hi-Z Output
(2)
Accesses to DDRB Read/Write DDRB[7:6, 3:0] DDRB[7:6, 3:0]
Accesses to PTB Read Pin PTB[7:6, 3:0] Write PTB[7:6, 3:0](3) PTB[7:6, 3:0]
X
1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect the input.
9.3.3 Port B High Current Drive Control Register (HDB)
The port-B high current drive control register (HDB) controls the high current drive capability on PTB[3:2]. Each bit is individually configurable and requires that the data direction register, DDRB, bit be configured as an output.
Address: Read: Write: Reset: 0 0 0 0 $000C Bit 7 0 6 0 5 0 4 0 3 HDB3 0 2 HDB2 0 1 0 0 Bit 0 0 0
Figure 9-8. Port B High Current Drive Control Register (HDB) HDB[3:2] -- Port B High Current Drive Enable Bits These read/write bits are software programmable to enable the direct LED drive on an output port pin. 1 = Corresponding port B pin is configured to high current sink direct LED drive. 0 = Corresponding port B pin is configured to standard drive
9.4 Port C
Port C is an 8-bit special function port that shares five of its port pins with the liquid crystal display (LCD) driver module. NOTE PTC4-PTC5 pins are not available on 44-pin package.
9.4.1 Port C Data Register (PTC)
The port C data register contains a data latch for each of the eight port C pins.
Address: Read: Write: Reset: Alternative Function: FP24 $0002 Bit 7 PTC7 6 PTC6 5 PTC5 4 PTC4 3 PTC3 2 PTC2 1 PTC1 Bit 0 PTC0
Unaffected by reset FP23 FP22 FP21 FP20 FP19
Figure 9-9. Port C Data Register (PTC)
MC68HC08LT8 Data Sheet, Rev. 1 100 Freescale Semiconductor
Port C
PTC[7:0] -- Port C Data Bits These read/write bits are software programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. FP[24:19] -- LCD Driver Frontplanes 24-19 FP[24:19] are pins used for the frontplane output of the LCD driver module. The enable bits, PCEH and PCEL, in the CONFIG2 register, and LCDE bit in the LCDCR register determine whether the PTC5/FP24-PTC4/FP23 and PTC3/FP22-PTC0/FP19 pins are LCD frontplane driver pins or general-purpose I/O pins. See Chapter 8 Liquid Crystal Display (LCD) Driver.
9.4.2 Data Direction Register C (DDRC)
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. NOTE For devices packaged in a 44-pin package, PTC4-PTC5 are not connected. DDRC4:5 should be set to a 1 to configure PTC4-PTC5 as outputs.
Address: Read: Write: Reset: $0006 Bit 7 DDRC7 0 6 DDRC6 0 5 DDRC5 0 4 DDRC4 0 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0
Figure 9-10. Data Direction Register C (DDRC) DDRC[7:0] -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 9-11 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTCx PTCx DDRCx
READ PTC ($0002)
Figure 9-11. Port C I/O Circuit
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 101
Input/Output (I/O) Ports
When DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 9-4 summarizes the operation of the port C pins.
Table 9-4. Port C Pin Functions
DDRC Bit 0 1 Accesses to DDRC PTC Bit X(1) X I/O Pin Mode Read/Write Input, Hi-Z(2) Output DDRC[7:0] DDRC[7:0] Read Pin PTC[7:0] Write Accesses to PTC
PTC[7:0](3)
PTC[7:0]
1. X = don't care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
9.5 Port D
Port D is an 8-bit special function port that shares all of its port pins with the liquid crystal display (LCD) driver module.
9.5.1 Port D Data Register (PTD)
The port D data register contains a data latch for each of the eight port D pins.
Address: Read: Write: Reset: Alternative Function: FP18 FP17 FP16 $0003 Bit 7 PTD7 6 PTD6 5 PTD5 4 PTD4 3 PTD3 2 PTD2 1 PTD1 Bit 0 PTD0
Unaffected by reset FP15 FP14 FP13 FP12 FP11
Figure 9-12. Port D Data Register (PTD) PTD[7:0] -- Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. FP[18:11] -- LCD Driver Frontplanes 18-11 FP[18:11] are pins used for the frontplane output of the LCD driver module. The enable bit, PDE, in the CONFIG2 register and LCDE bit in the LCDCR register, determines whether the PTD7/FP18-PTD0/FP11 pins are LCD frontplane driver pins or general-purpose I/O pins. See Chapter 8 Liquid Crystal Display (LCD) Driver.
MC68HC08LT8 Data Sheet, Rev. 1 102 Freescale Semiconductor
Port D
9.5.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0007 Bit 7 DDRD7 0 6 DDRD6 0 5 DDRD5 0 4 DDRD4 0 3 DDRD3 0 2 DDRD2 0 1 DDRD1 0 Bit 0 DDRD0 0
Figure 9-13. Data Direction Register D (DDRD) DDRD[7:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 9-14 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx DDRDx
READ PTD ($0003)
Figure 9-14. Port D I/O Circuit When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 9-5 summarizes the operation of the port D pins. Table 9-5. Port D Pin Functions
DDRD Bit 0 1 Accesses to DDRD PTD Bit X(1) X I/O Pin Mode Read/Write Input, Hi-Z(2) Output DDRD[7:0] DDRD[7:0] Read Pin PTD[7:0] Write Accesses to PTD
PTD[7:0](3)
PTD[7:0]
1. X = don't care; except. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 103
Input/Output (I/O) Ports
9.6 Port E
Port E is an 8-bit special function port that shares all of its port pins with the liquid crystal display (LCD) driver module.
9.6.1 Port E Data Register (PTE)
The port E data register contains a data latch for each of the eight port E pins.
Address: Read: Write: Reset: Alternative Function: FP10 FP9 FP8 $0009 Bit 7 PTE7 6 PTE6 5 PTE5 4 PTE4 3 PTE3 2 PTE2 1 PTE1 Bit 0 PTE0
Unaffected by reset FP7 FP6 FP5 FP4 FP3
Figure 9-15. Port E Data Register (PTE) PTE[7:0] -- Port E Data Bits These read/write bits are software programmable. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. Reset has no effect on port E data. FP[10:3] -- LCD Driver Frontplanes 10-3 FP[10:3] are pins used for the frontplane output of the LCD driver module. The enable bit, PEE, in the CONFIG2 register and LCDE bit in the LCDCR register, determines whether the PTE7/FP10-PTE0/FP3 pins are LCD frontplane driver pins or general-purpose I/O pins. See Chapter 8 Liquid Crystal Display (LCD) Driver.
9.6.2 Data Direction Register E (DDRE)
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0008 Bit 7 DDRE7 0 6 DDRE6 0 5 DDRE5 0 4 DDRE4 0 3 DDRE3 0 2 DDRE2 0 1 DDRE1 0 Bit 0 DDRE0 0
Figure 9-16. Data Direction Register E (DDRE) DDRE[7:0] -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 9-14 shows the port E I/O logic.
MC68HC08LT8 Data Sheet, Rev. 1 104 Freescale Semiconductor
Port E
READ DDRE ($0008)
WRITE DDRE ($0008) INTERNAL DATA BUS RESET WRITE PTE ($0009) PTEx PTEx DDREx
READ PTE ($0009)
Figure 9-17. Port E I/O Circuit When DDREx is a logic 1, reading address $0009 reads the PTEx data latch. When DDREx is a logic 0, reading address $0009 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 9-5 summarizes the operation of the port E pins. Table 9-6. Port E Pin Functions
DDRE Bit 0 1 Accesses to DDRE PTE Bit X(1) X I/O Pin Mode Read/Write Input, Hi-Z(2) Output DDRE[7:0] DDRE[7:0] Read Pin PTE[7:0] Write Accesses to PTE
PTE[7:0](3)
PTE[7:0]
1. X = don't care; except. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 105
Input/Output (I/O) Ports
MC68HC08LT8 Data Sheet, Rev. 1 106 Freescale Semiconductor
Chapter 10 External Interrupt (IRQ)
10.1 Introduction
The external interrupt (IRQ) module provides a maskable interrupt input.
10.2 Features
Features of the IRQ module include the following: * A dedicated external interrupt pin (IRQ) * IRQ interrupt control bits * Hysteresis buffer * Spike filter * Programmable edge-only or edge and level interrupt sensitivity * Automatic interrupt acknowledge * Selectable internal pullup resistor
10.3 Functional Description
A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 10-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. * Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (INTSCR). Writing a logic one to the ACK bit clears the IRQ latch. * Reset -- A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge or falling-edge and low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: * Vector fetch or software clear * Return of the interrupt pin to logic one
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 107
External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See 4.5 Exception Control.)
RESET ACK INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE IRQ TO CPU FOR BIL/BIH INSTRUCTIONS
VDD D CLR Q SYNCHRONIZER CK
IRQF IRQ INTERRUPT REQUEST
IMASK
MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 10-1. IRQ Module Block Diagram
Addr. $001E Register Name IRQ Status and Control Read: Register Write: (INTSCR) Reset: Bit 7 0 0 6 0 0 = Unimplemented 5 0 0 4 0 0 3 IRQF 0 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
Figure 10-2. IRQ I/O Register Summary
MC68HC08LT8 Data Sheet, Rev. 1 108 Freescale Semiconductor
IRQ Module During Break Interrupts
10.3.1 IRQ Pin
A logic zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. * Return of the IRQ pin to logic one -- As long as the IRQ pin is at logic zero, IRQ remains active. The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch.d to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. NOTE An internal pull-up resistor to VDD is connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
10.4 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Chapter 4 System Integration Module (SIM).) To allow software to clear the IRQ latch during a break interrupt, write a logic one to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 109
External Interrupt (IRQ)
10.5 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR has the following functions: * Shows the state of the IRQ flag * Clears the IRQ latch * Masks IRQ and interrupt request * Controls triggering sensitivity of the IRQ interrupt pin
Address: $001E Bit 7 Read: Write: Reset: 0 0 0 0 0 = Unimplemented 0 6 0 5 0 4 0 3 IRQF 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
Figure 10-3. IRQ Status and Control Register (INTSCR) IRQF -- IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic one to this write-only bit clears the IRQ latch. ACK always reads as logic zero. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic one to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
MC68HC08LT8 Data Sheet, Rev. 1 110 Freescale Semiconductor
Chapter 11 Keyboard Interrupt Module (KBI)
11.1 Introduction
The keyboard interrupt module (KBI) provides four independently maskable external interrupts which are accessible via PTA0-PTA3. When a port pin is enabled for keyboard interrupt function, an internal pull-up device is also enabled on the pin.
11.2 Features
Features of the keyboard interrupt module include the following: * Four keyboard interrupt pins with pull-up devices * Separate keyboard interrupt enable bits and one keyboard interrupt mask * Programmable edge-only or edge- and level- interrupt sensitivity * Exit from low-power modes
Addr. $001B Register Name Keyboard Status and Read: Control Register Write: (KBSCR) Reset: Keyboard Interrupt Read: Enable Register Write: (KBIER) Reset: Bit 7 0 0 0 0 6 0 0 0 0 = Unimplemented 5 0 0 0 0 4 0 0 0 0 3 KEYF 0 KBIE3 0 2 0 ACKK 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0
$001C
Figure 11-1. KBI I/O Register Summary
11.3 I/O Pins
The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins are listed in Table 11-1. The generic pin name appear in the text that follows. Table 11-1. Pin Name Conventions
KBI Generic Pin Name KBI0-KBI3 Full MCU Pin Name PTA0/KBI0-PTA3/KBI3 Pin Selected for KBI Function by KBIEx Bit in KBIER KBIE0-KBIE3
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 111
Keyboard Interrupt Module (KBI)
11.4 Functional Description
NOTE: To prevent false interrupts, user should use software to debounce keyboard interrupt inputs. INTERNAL BUS
KBI0
VDD . KBIE0 . . D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER KEYBOARD INTERRUPT REQUEST
CK
TO PULLUP ENABLE KEYBOARD INTERRUPT FF IMASKK
KBI3
MODEK KBIE3 TO PULLUP ENABLE
Figure 11-2. Keyboard Interrupt Block Diagram Writing to the KBIE3-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also enables its internal pull-up device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. * If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. * Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order.
MC68HC08LT8 Data Sheet, Rev. 1 112 Freescale Semiconductor
Keyboard Interrupt Registers
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, disable the pull-up device, use the data direction register to configure the pin as an input and then read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
11.4.1 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A. 2. Write logic 1's to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
11.5 Keyboard Interrupt Registers
Two registers control the operation of the keyboard interrupt module: * Keyboard status and control register * Keyboard interrupt enable register
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 113
Keyboard Interrupt Module (KBI)
11.5.1 Keyboard Status and Control Register
* * * * Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
Address: $001B Bit 7 Read: Write: Reset: 0 0 0 0 0 = Unimplemented 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 1 IMASKK 0 Bit 0 MODEK 0
Figure 11-3. Keyboard Status and Control Register (KBSCR) KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port A. ACKK always reads as logic 0. Reset clears ACKK. IMASKK-- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
MC68HC08LT8 Data Sheet, Rev. 1 114 Freescale Semiconductor
Low-Power Modes
11.5.2 Keyboard Interrupt Enable Register
The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a keyboard interrupt pin.
Address: $001C Bit 7 Read: Write: Reset: 0 0 0 0 0 6 0 5 0 4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0
Figure 11-4. Keyboard Interrupt Enable Register (KBIER) KBIE3-KBIE0 -- Port-A Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port-A to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin
11.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
11.6.1 Wait Mode
The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
11.6.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
11.7 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 115
Keyboard Interrupt Module (KBI)
MC68HC08LT8 Data Sheet, Rev. 1 116 Freescale Semiconductor
Chapter 12 Computer Operating Properly (COP)
12.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG1 register.
12.2 Functional Description
Figure 12-1 shows the structure of the COP module.
SIM CGMXCLK 12-BIT SIM COUNTER SIM RESET CIRCUIT RESET STATUS REGISTER
CLEAR ALL STAGES
CLEAR STAGES 5-12
INTERNAL RESET SOURCES(1) RESET VECTOR FETCH COPCTL WRITE
COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) CLEAR COP COUNTER
Figure 12-1. COP Block Diagram
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 117
COP TIMEOUT
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 CGMXCLK cycles; depending on the state of the COP rate select bit, COPRS, in CONFIG1 register. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter. NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 x CGMXCLK cycles and sets the COP bit in the reset status register (RSR). (See 4.7.2 Reset Status Register (RSR).). NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
12.3 I/O Signals
The following paragraphs describe the signals shown in Figure 12-1.
12.3.1 CMGXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
12.3.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 12.4 COP Control Register) clears the COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector.
12.3.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 x CGMXCLK cycles after power-up.
12.3.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
12.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter.
12.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG1 register. (See 3.3 Configuration Register 1 (CONFIG1).)
MC68HC08LT8 Data Sheet, Rev. 1 118 Freescale Semiconductor
COP Control Register
12.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1. (See 3.3 Configuration Register 1 (CONFIG1).)
12.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 Low byte of reset vector Clear COP counter Unaffected by reset
Figure 12-2. COP Control Register (COPCTL)
12.5 Interrupts
The COP does not generate CPU interrupt requests.
12.6 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.
12.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
12.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
12.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
12.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 119
Computer Operating Properly (COP)
MC68HC08LT8 Data Sheet, Rev. 1 120 Freescale Semiconductor
Chapter 13 Low-Voltage Inhibit (LVI)
13.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
13.2 Features
Features of the LVI module include: * Programmable LVI interrupt and reset * Selectable LVI trip voltage * Programmable stop mode operation
13.3 Functional Description
Figure 13-1 shows the structure of the LVI module.
VDD STOP INSTRUCTION LVISTOP
DEFAULT ENABLED FROM CONFIG1 FROM CONFIG1
LVIRSTD LVIPWRD
FROM CONFIG1
LOW VDD DETECTOR
VDD > VTRIPR = 0 VDD VTRIPF = 1
FROM LVISR
LVI RESET
LVIIE LVISEL[1:0]
FROM CONFIG2
EDGE DETECT LATCH CLR
LVI INTERRUPT REQUEST
LVIOUT
TO LVISR
LVIIACK
FROM LVISR
LVIIF
TO LVISR
Figure 13-1. LVI Module Block Diagram
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 121
Low-Voltage Inhibit (LVI)
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. The LVI trip point selection bits, LVISEL[1:0], select the trip point voltage, VTRIPF, to be configured for 5V or 3V operation. The actual trip points are shown in Chapter 16 Electrical Specifications. Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever the LVIOUT bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0). NOTE After a power-on reset (POR) the LVI's default mode of operation is 3V. If a 5V system is used, the user must modified the LVISEL[1:0] bits to raise the trip point to 5V operation. Note that this must be done after every power-on reset since the default will revert back to 3V mode after each power-on reset. If the VDD supply is below the 3V mode trip voltage when POR is released, the MCU will immediately go into reset. The LVI in this case will hold the MCU in reset until either VDD goes above the rising 3V trip point, VTRIPR, which will release reset or VDD decreases to approximately 0V which will re-trigger the power-on reset. LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the configuration registers. See Section 5. Configuration Registers (CONFIG) for details of the LVI's configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 4.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). The LVIIE, LVIIF, and LVIIACK bits in the LVISR control LVI interrupt functions. An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
13.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit, or by setting the LVI interrupt enable bit, LVIIE, to enable interrupt requests. In the configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets. The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes state (toggles). When LVIF is set, a CPU interrupt request is generated if the LVIIE is also set. In the LVI interrupt service subroutine, LVIIF bit can be cleared by writing a logic 1 to the LVI interrupt acknowledge bit, LVIIACK.
13.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register 1 (CONFIG1), the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets. If LVIIE is set to enable LVI interrupts when LVIRSTD is cleared, LVI reset has a higher priority over LVI interrupt. In this case, when VDD falls below the VTRIPF level, an LVI reset will occur, and the LVIIE bit will be cleared.
MC68HC08LT8 Data Sheet, Rev. 1 122 Freescale Semiconductor
LVI Status Register
13.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS.
13.3.4 LVI Trip Selection
The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select whether the LVI is configured for 5V or 3 V operation. (See Chapter 3 Configuration Register (CONFIG).) NOTE The MCU is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF [5V] or VTRIPF [3V]) may be lower than this. (See Chapter 16 Electrical Specifications for the actual trip point voltages.)
13.4 LVI Status Register
The LVI status register (LVISR) controls LVI interrupt functions and indicates if the VDD voltage was detected below the VTRIPF level.
Address: Read: Write: Reset: 0 $FE0F Bit 7 LVIOUT 6 LVIIE 0 = Unimplemented 5 LVIIF 0 4 0 LVIIACK 0 0 0 0 0 3 0 2 0 1 0 Bit 0 0
Figure 13-2. LVI Status Register (LVISR) LVIOUT -- LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage (see Table 13-1). Reset clears the LVIOUT bit.
Table 13-1. LVIOUT Bit Indication
VDD VDD > VTRIPR VDD < VTRIPF VTRIPF < VDD < VTRIPR LVIOUT 0 1 Previous value
LVIIE -- LVI Interrupt Enable Bit This read/write bit enables the LVIIF bit to generate CPU interrupt requests. Reset clears the LVIIE bit. 1 = LVIIF can generate CPU interrupt requests 0 = LVIIF cannot generate CPU interrupt requests
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 123
Low-Voltage Inhibit (LVI)
LVIIF -- LVI Interrupt Flag This clearable, read-only flag is set whenever the LVIOUT bit toggles. Reset clears the LVIIF bit. 1 = LVIOUT has toggled 0 = LVIOUT has not toggled LVIIACK -- LVI Interrupt Acknowledge Bit Writing a logic 1 to this write-only bit clears the LVI interrupt flag, LVIIF. LVIIACK always reads as logic 0. 1 = Clears LVIIF bit 0 = No effect
13.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
13.5.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets or interrupts, the LVI module can generate a reset or an interrupt and bring the MCU out of wait mode.
13.5.2 Stop Mode
If enabled in stop mode (LVISTOP = 1), the LVI module remains active in stop mode. If enabled to generate resets or interrupts, the LVI module can generate a reset or an interrupt and bring the MCU out of stop mode. NOTE If enabled to generate both resets and interrupts, there will be no LVI interrupts, as resets have a higher priority.
MC68HC08LT8 Data Sheet, Rev. 1 124 Freescale Semiconductor
Chapter 14 Central Processor Unit (CPU)
14.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
14.2 Features
Features of the CPU include: * Object code fully upward-compatible with M68HC05 Family * 16-bit stack pointer with stack manipulation instructions * 16-bit index register with x-register manipulation instructions * 4-MHz CPU internal bus frequency * 64-Kbyte program/data memory space * 16 addressing modes * Memory-to-memory data moves without using accumulator * Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions * Enhanced binary-coded decimal (BCD) data handling * Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes * Low-power stop and wait modes
14.3 CPU Registers
Figure 14-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 125
Central Processor Unit (CPU)
7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 14-1. CPU Registers
14.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 14-2. Accumulator (A)
14.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X X = Indeterminate 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 14-3. Index Register (H:X)
MC68HC08LT8 Data Sheet, Rev. 1 126 Freescale Semiconductor
CPU Registers
14.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 14-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
14.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 14-5. Program Counter (PC)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 127
Central Processor Unit (CPU)
14.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: Write: Reset: V X X = Indeterminate 6 1 1 5 1 1 4 H X 3 I 1 2 N X 1 Z X Bit 0 C X
Figure 14-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result
MC68HC08LT8 Data Sheet, Rev. 1 128 Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z -- Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
14.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
14.5.1 Wait Mode
The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock
14.5.2 Stop Mode
The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
14.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by: * Loading the instruction register with the SWI instruction * Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 129
Central Processor Unit (CPU)
14.7 Instruction Set Summary
Table 14-1 provides a summary of the M68HC08 instruction set. Table 14-1. Instruction Set Summary (Sheet 1 of 6)
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Operation
Description
VH I NZC
Add with Carry
A (A) + (M) + (C)
-
IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff
Add without Carry
A (A) + (M)
-
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24 11 13 15 17 19 1B 1D 1F 25 27 90 92 28 29 22 rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr
Arithmetic Shift Right
b7 b0
C
--
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL - - - - - - REL
BCLR n, opr
Clear Bit n in M
Mn 0
BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 - - - - - - REL - - - - - - REL - - - - - - REL
3 3
MC68HC08LT8 Data Sheet, Rev. 1 130 Freescale Semiconductor
Cycles
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 3 3 3 3 3
Effect on CCR
Operand
Instruction Set Summary
Table 14-1. Instruction Set Summary (Sheet 2 of 6)
Address Mode Opcode Source Form
BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
VH I NZC
- - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT - IX2 IX1 IX SP1 SP2
24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A
rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr
Bit Test
(A) & (M)
0--
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
-----
BRN rel
Branch Never
PC (PC) + 2
- - - - - - REL
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
-----
BSET n,opr
Set Bit n in M
Mn 1
DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR IMM - - - - - - IMM IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI Clear Carry Bit Clear Interrupt Mask
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 131
Cycles
3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2
Effect on CCR
Operand
Central Processor Unit (CPU)
Table 14-1. Instruction Set Summary (Sheet 3 of 6)
Address Mode Opcode Source Form
CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Operation
Description
M $00 A $00 X $00 H $00 M $00 M $00 M $00
VH I NZC
Clear
DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR IMM DIR EXT IX2 IX1 IX SP1 SP2 INH
3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff
Compare A with M
(A) - (M)
--
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
0--
33 dd 43 53 63 ff 73 9E63 ff 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr ii ii+1 dd ii dd hh ll ee ff ff ff ee ff
Compare H:X with M
--
Compare X with M
(X) - (M)
--
Decimal Adjust A
(A)10
U--
DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP
A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 - - - - - - INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - IX1 IX SP1 INH IMM DIR EXT - IX2 IX1 IX SP1 SP2 DIR INH - INH IX1 IX SP1
Decrement
--
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff
Divide
----
Exclusive OR M with A
A (A M)
0--
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
--
3C dd 4C 5C 6C ff 7C 9E6C ff
MC68HC08LT8 Data Sheet, Rev. 1 132 Freescale Semiconductor
Cycles
3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5 4 1 1 4 3 5
Effect on CCR
Operand
Instruction Set Summary
Table 14-1. Instruction Set Summary (Sheet 4 of 6)
Address Mode Opcode Source Form
JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX
Operation
Description
VH I NZC
PC Jump Address
Jump
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 - IX1 IX SP1 SP2 - IMM DIR
BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE
dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
Load H:X from M
H:X (M:M + 1)
0--
Load X from M
X (M)
0--
IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 DD DIX+ - IMD IX+D DIR INH INH IX1 IX SP1
Logical Shift Left (Same as ASL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd
Logical Shift Right
0 b7 b0
C
--0
Move Unsigned multiply
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
0--
- 0 - - - 0 INH
Negate (Two's Complement)
--
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
Push A onto Stack Push H onto Stack Push X onto Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1
- - - - - - INH - - - - - - INH - - - - - - INH
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 133
Cycles
2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3 2 3 4 4 3 2 4 5 2 2 2
Effect on CCR
Operand
Central Processor Unit (CPU)
Table 14-1. Instruction Set Summary (Sheet 5 of 6)
Address Mode Opcode Source Form
PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Operation
Pull A from Stack Pull H from Stack Pull X from Stack
Description
SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
VH I NZC
- - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
86 8A 88 39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
Rotate Left through Carry
C b7 b0
--
Rotate Right through Carry
b7 b0
C
--
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
- - - - - - INH
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 IX1 IX SP1 SP2
81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff
Subtract with Carry
A (A) - (M) - (C)
--
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable Interrupts, Stop Processing, Refer to MCU Documentation
(M:M + 1) (H:X) I 0; Stop Processing
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
Store X in M
M (X)
0--
Subtract
A (A) - (M)
--
MC68HC08LT8 Data Sheet, Rev. 1 134 Freescale Semiconductor
Cycles
2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Effect on CCR
Operand
Opcode Map
Table 14-1. Instruction Set Summary (Sheet 6 of 6)
Address Mode Opcode Source Form Operation Description
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
VH I NZC
SWI
Software Interrupt
- - 1 - - - INH
83
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS WAIT A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH - IX1 IX SP1
84 97 85 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94 8F
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP Enable Interrupts; Wait for Interrupt
H:X (SP) + 1 A (X) (SP) (H:X) - 1 I bit 0; Inhibit CPU clocking until interrupted n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
- - - - - - INH - - - - - - INH - - - - - - INH - - 0 - - - INH
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) # ? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
14.8 Opcode Map
See Table 14-2.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 135
Cycles
9 2 1 1 3 1 1 3 2 4 2 1 2 1
Effect on CCR
Operand
136
Bit Manipulation DIR DIR
MSB LSB
Central Processor Unit (CPU)
Table 14-2. Opcode Map
Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL DIR 3 INH 4 Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 SP1 9E6 IX 7 Control INH INH 8 9 IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM DIR B EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT Register/Memory IX2 SP2 D 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 9ED 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 IX1 E SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 IX F 0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2 3 4
5 6 7 8 9 A B C D E
F
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Chapter 15 Development Support
15.1 Introduction
This section describes the break module, the monitor module (MON), and the monitor mode entry methods.
15.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. Features include: * Accessible input/output (I/O) registers during the break Interrupt * Central processor unit (CPU) generated break interrupts * Software-generated break interrupts * Computer operating properly (COP) disabling during break interrupts
15.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. * Software writes a logic one to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 15-1 shows the structure of the break module. When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: * Loading the instruction register with the SWI instruction * Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 137
Development Support
IAB[15:8]
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BKPT (TO SIM)
IAB[7:0]
Figure 15-1. Break Module Block Diagram The break interrupt timing is: * When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. * When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. * When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed. By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be generated continuously. CAUTION A break address should be placed at the address of the instruction opcode. When software does not change the break address and clears the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 15.2.1.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 4.7.3 SIM Break Flag Control Register and the "Break Interrupts" subsection for each module.) 15.2.1.2 TIM During Break Interrupts A break interrupt stops the timer counter. 15.2.1.3 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC08LT8 Data Sheet, Rev. 1 138 Freescale Semiconductor
Break Module (BRK)
15.2.2 Break Module Registers
These registers control and monitor operation of the break module: * Break status and control register (BRKSCR) * Break address register high (BRKH) * Break address register low (BRKL) * Break status register (BSR) * Break flag control register (BFCR) 15.2.2.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits.
Address: $FE0E Bit 7 Read: Write: Reset: BRKE 0 6 BRKA 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 15-2. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic zero to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic one to BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 139
Development Support
15.2.2.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: $FE0C
Bit 7
Read: Write: Reset: Bit 15 0
6
14 0
5
13 0
4
12 0
3
11 0
2
10 0
1
9 0
Bit 0
Bit 8 0
Figure 15-3. Break Address Register High (BRKH)
Address: $FE0D Bit 7 Read: Write: Reset: Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
Figure 15-4. Break Address Register Low (BRKL) 15.2.2.3 Break Status Register The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address: $FE00 Bit 7 Read: Write: Reset: R = Reserved R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) 0 1. Writing a logic zero clears SBSW. Bit 0 R
Figure 15-5. Break Status Register (BSR) SBSW -- SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it.
MC68HC08LT8 Data Sheet, Rev. 1 140 Freescale Semiconductor
Break Module (BRK)
15.2.2.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: Write: Reset: BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 15-6. Break Flag Control Register (BFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
15.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes. However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 141
Development Support
15.3 Monitor Module (MON)
The monitor module allows complete testing of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Features of the monitor module include: * Normal user-mode pin functionality * One pin dedicated to serial communication between MCU and host computer * Standard non-return-to-zero (NRZ) communication with host computer * Standard communication baud rate (9600 @ 2.4576-MHz internal operating frequency) * Execution of code in random-access memory (RAM) or ROM * ROM security feature(1) * Use of external 4.9152MHz or 9.8304MHz oscillator to generate internal operating frequency of 2.4576 MHz * Normal monitor mode entry if VTST is applied to IRQ
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the ROM difficult for unauthorized users. MC68HC08LT8 Data Sheet, Rev. 1 142 Freescale Semiconductor
Chapter 16 Electrical Specifications
16.1 Introduction
This section contains electrical and timing specifications.
16.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.5 5-V DC Electrical Characteristics and 16.6 3-V DC Electrical Characteristics for guaranteed operating conditions. Table 16-1. Absolute Maximum Ratings
Characteristic(1) Supply voltage LCD voltage Input voltage Mode entry voltage, IRQ pin Maximum current per pin excluding VDD and VSS Storage temperature Maximum current out of VSS Maximum current into VDD 1. Voltages referenced to VSS. Symbol VDD VLCD VIN VTST I TSTG IMVSS IMVDD Value -0.3 to +6.0 VSS to +6.0 VSS -0.3 to VDD +0.3 VSS -0.3 to +8.5 25 -55 to +150 100 100 V V mA C mA mA Unit V
NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.)
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 143
Electrical Specifications
16.3 Functional Operating Range
Table 16-2. Operating Range
Characteristic Operating temperature range Operating voltage range LCD voltage Symbol TA (TL to TH) VDD VLCD Value - 40 to +85 1.8 to 5.5(1) VSS to VDD Unit C V V
1. For normal operation, user should ensure that the device supply voltage is above the LVI trip voltage.
16.4 Thermal Characteristics
Table 16-3. Thermal Characteristics
Characteristic Thermal resistance 44-pin LQFP I/O pin power dissipation Power dissipation(1) Symbol JA PI/O PD Value Unit C/W W W
85 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA)
Constant(2) Average junction temperature
K TJ
W/C C
1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC08LT8 Data Sheet, Rev. 1 144 Freescale Semiconductor
5-V DC Electrical Characteristics
16.5 5-V DC Electrical Characteristics
Table 16-4. DC Electrical Characteristics (5V)
Characteristic(1) Output high voltage (ILOAD = -1.6mA) All ports Output low voltage (ILOAD = 2mA) All ports except PTB2-PTB3 (ILOAD = 15mA) PTB2-PTB3 Input high voltage All ports, RST, IRQ, OSC1 Input low voltage All ports, RST, IRQ, OSC1 VDD supply current, fOP = 4MHz (RLCD = 146k) Run(3) with all modules on Wait(4) with all modules off (except PPI, LCD, and LVI) Stop(5) -40 to 85C (All modules off) 25C (XTAL, LCD, PPI enabled) 25C (XTAL, LCD, PPI, LVI enabled) 25C (XTAL, LCD, PPI, LVI, OSC enabled) Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate
(7)
Symbol VOH
Min VDD -0.7
Typ(2) --
Max --
Unit V
VOL
-- 0.7 x VDD VSS
--
0.7
V
VIH VIL
-- --
VDD 0.3 x VDD
V V
--
5
12
mA
IDD
-- -- -- -- --
3 0.3 25 175 1.5 -- -- -- -- -- -- -- 100 4.20 4.30 100
6 1 50 190 3 10 1 12 8 -- -- 9.1 200 4.50 4.60 --
mA A A A mA A A pF mV V/ms V k V V mV
IIL IIN COUT CIN VPOR RPOR VTST RPU VTRIPF VTRIPR VHYS
-- -- -- -- 750 0.035 VDD + 2.5 50 3.90 3.95 --
Monitor mode entry voltage Pullup resistors(8) PTA0-PTA3 as KBI0-KBI3, RST, IRQ Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Low-voltage inhibit reset/recovery hysteresis
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU is measured at VDD = 5.0V.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 145
Electrical Specifications
16.6 3-V DC Electrical Characteristics
Table 16-5. DC Electrical Characteristics (3V)
Characteristic(1) Output high voltage (ILOAD = -0.4 mA) All ports Output low voltage (ILOAD = 0.5mA) All ports except PTB2-PTB3 (ILOAD = 10mA) PTB2-PTB3 Input high voltage All ports, RST, IRQ, OSC1 Input low voltage All ports, RST, IRQ, OSC1 VDD supply current, fOP = 2MHz (RLCD = 146k) Run(3) with all modules on Wait(4) with all modules off, except PPI, LCD, and LVI Stop(5) -40 to 85C (All modules off) 25C (XTAL, LCD, PPI enabled) 25C (XTAL, LCD, PPI, LVI enabled) 25C (XTAL, LCD, PPI, LVI, OSC enabled) Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate
(7)
Symbol VOH
Min VDD - 0.7
Typ(2) --
Max --
Unit V
VOL
-- 0.7 x VDD VSS
--
0.7
V
VIH VIL
-- --
VDD 0.3 x VDD
V V
--
3
6
mA
IDD
-- -- -- -- --
2 0.2 7 150 1 -- -- -- -- -- -- -- 100 1.90 1.97 70
4 1 25 165 2 10 1 12 8 -- -- 9.1 200 2.00 2.10 --
mA A A A mA A A pF mV V/ms V k V V mV
IIL IIN COUT CIN VPOR RPOR VTST RPU VTRIPF VTRIPR VHYS
-- -- -- -- 750 0.02 VDD + 2.5 50 1.80 1.85 --
Monitor mode entry voltage Pullup resistors(8) PTA0-PTA3 as KBI0-KBI3, RST, IRQ Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Low-voltage inhibit reset/recovery hysteresis
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 2 MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 2 MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU is measured at VDD = 5.0V.
MC68HC08LT8 Data Sheet, Rev. 1 146 Freescale Semiconductor
2-V DC Electrical Characteristics
16.7 2-V DC Electrical Characteristics
Table 16-6. DC Electrical Characteristics (2V)
Characteristic(1) Output high voltage (ILOAD = -0.4 mA) All ports Output low voltage (ILOAD = 0.5mA) All ports except PTB2-PTB3 (ILOAD = 8mA) PTB2-PTB3 Input high voltage All ports, RST, IRQ, OSC1 Input low voltage All ports, RST, IRQ, OSC1 VDD supply current, fOP = 1MHz (RLCD = 146k) Run(3) with all modules on Wait(4) with all modules off, except PPI, LCD, and LVI Stop(5) -40 to 85C (All modules off) 25C (XTAL, LCD, PPI enabled) 25C (XTAL, LCD, PPI, LVI enabled) 25C (XTAL, LCD, PPI, LVI, OSC enabled) Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR rearm voltage(6) POR rise time ramp rate
(7)
Symbol VOH
Min VDD - 0.5
Typ(2) --
Max --
Unit V
VOL
-- 0.7 x VDD VSS
--
0.5
V
VIH VIL
-- --
VDD 0.3 x VDD
V V
--
0.8
2
mA
IDD
-- -- -- -- --
0.6 0.2 5 147 0.5 -- -- -- -- -- -- -- 100
1.8 1 15 155 1 10 1 12 8 -- -- 9.1 200
mA A A A mA A A pF mV V/ms V k
IIL IIN COUT CIN VPOR RPOR VTST RPU
-- -- -- -- 750 0.02 VDD + 2.5 50
Monitor mode entry voltage Pullup resistors(8) PTA0-PTA3 as KBI0-KBI3, RST, IRQ
1. VDD = 1.8 to 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source (fOP = 1 MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 1 MHz). All inputs 0.2V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU is measured at VDD = 5.0V.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 147
Electrical Specifications
16.8 5-V Control Timing
Table 16-7. Control Timing (5V)
Characteristic(1) Internal operating frequency RST input pulse width low(2) IRQ interrupt pulse width low (edge-triggered)(3) IRQ interrupt pulse period(3) Symbol fOP tIRL tILIH tILIL Min -- 100 100 Note(4) Max 4 -- -- -- Unit MHz ns ns tCYC
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. 3. Values are based on characterization results, not tested in production. 4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
16.9 3-V Control Timing
Table 16-8. Control Timing (3V)
Characteristic(1) Internal operating frequency RST input pulse width low(2) IRQ interrupt pulse width low (edge-triggered)(3) IRQ interrupt pulse period(3) Symbol fOP tIRL tILIH tILIL Min -- 250 250 Note(4) Max 2 -- -- -- Unit MHz ns ns tCYC
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. 3. Values are based on characterization results, not tested in production. 4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
16.10 2-V Control Timing
Table 16-9. Control Timing (2V)
Characteristic(1) Internal operating frequency RST input pulse width low(2) IRQ interrupt pulse width low (edge-triggered)(3) IRQ interrupt pulse period(3) Symbol fOP tIRL tILIH tILIL Min -- 500 500 Note(4) Max 1 -- -- -- Unit MHz ns ns tCYC
1. VDD = 1.8 to 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. 3. Values are based on characterization results, not tested in production. 4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
MC68HC08LT8 Data Sheet, Rev. 1 148 Freescale Semiconductor
Oscillator Characteristics
tRL RST tILIL tILIH IRQ
Figure 16-1. RST and IRQ Timing
16.11 Oscillator Characteristics
Table 16-10. Oscillator Specifications
Characteristic Oscillator 1 on OSC1 and OSC2 (for system bus) External reference clock to OSC1 (1) Crystal reference frequency (2) Crystal load capacitance (3) Crystal fixed capacitance
(3)
Symbol fOSC fXTALCLK1 CL C1 C2 RB1 RS1 fXTALCLK2 CL C3 C4 RB2 RS2
Min
Typ
Max
Unit
dc 1M -- -- -- -- --
-- -- -- 18 18 4.7 0
16M 16M -- -- -- -- --
Hz Hz
pF pF M k
Crystal tuning capacitance (3) Feedback bias resistor Series resistor Oscillator 2 on XTAL1 and XTAL2 (for LCD and PPI) Crystal reference frequency (2) Crystal load capacitance
(3)
-- -- -- -- -- --
32.768k -- 10 10 10 10
-- -- -- -- -- --
Hz
Crystal fixed capacitance (3) Crystal tuning capacitance (3) Feedback bias resistor Series resistor
pF pF M k
1. No more than 10% duty cycle deviation from 50%. 2. Use fundamental mode only, do not use overtone crystals or overtone ceramic resonators. 3. Consult crystal vendor data sheet.
16.12 Timer Interface Module Characteristics
Table 16-11. Timer Interface Module Characteristics
Characteristic Input capture pulse width Symbol tTIH, tTIL Min 1/fOP Max -- Unit
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 149
Electrical Specifications
MC68HC08LT8 Data Sheet, Rev. 1 150 Freescale Semiconductor
Chapter 17 Ordering Information and Mechanical Specifications
17.1 Introduction
This section contains order numbers for the MC68HC08LT8. Dimensions are given for: * 44-pin low-profile quad flat pack (LQFP)
17.2 MC Order Numbers
These part numbers are generic numbers only. To place an order, ROM code must be submitted to the ROM Processing Center (RPC). Table 17-1. MC Order Numbers
MC Order Number MC68HC08LT8CFGE Operating Temperature Range -40 to +85 C Package 44-pin LQFP RoHS Compliant Yes
17.3 Package Dimensions
Refer to the following pages for detailed package dimensions.
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 151
Ordering Information and Mechanical Specifications
MC68HC08LT8 Data Sheet, Rev. 1 152 Freescale Semiconductor
Package Dimensions
MC68HC08LT8 Data Sheet, Rev. 1 Freescale Semiconductor 153
Ordering Information and Mechanical Specifications
MC68HC08LT8 Data Sheet, Rev. 1 154 Freescale Semiconductor
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MC68HC08LT8 Rev. 1, 3/2006

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